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 مراجع ودوائر وأعطال و شرح صيانة -CRT-LCD -plasma

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كاتب الموضوعرسالة
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مُساهمةموضوع: رد: مراجع ودوائر وأعطال و شرح صيانة -CRT-LCD -plasma   الجمعة أبريل 22, 2011 2:37 am

Chassis Sony BE-4, BE-4A



Adjustment is made with the full set up the TV or changing kineskopa.Regulirovki
conducted with nominal values ​​of supply voltages, unless otherwise indicated inoe.CONTRAST
80%, BRIGHTNESS 50%.


Adjustments are performed in the following order:

  1. Hit the beam
  2. Reduction of the rays
  3. SCREEN, black level, white balance, and subtsvetnost subyarkost.
  4. Focus.


[ندعوك للتسجيل في المنتدى أو التعريف بنفسك لمعاينة هذه الصورة]

Figure 1

Hit the beam

After demagnetization:

  1. To signal a white field.
  2. Switch to the red field.
  3. Move back and running through the magnets to adjust the color purity, so
    that the red color was at the center of the screen, and blue and green, located at
    edges.
  4. Move the OS forward and adjust so that the whole screen turned red.
  5. Switch signal in blue and green for verification.
  6. Secure OS screw.
  7. If the purity of color in the corners is not enough, adjust it using the disk
    magnets.


Reduction of the rays

  1. Before the beginning of information do the focus and adjust the size of the horizontal
    and vertical (H. SIZE, and V. SIZE)
  2. Set the brightness to minimum.
  3. The input is a generator of the image point.


Static mixing horizontally and vertically.

  1. H. STAT control, align the colored dots in the center of the screen (the reduction of
    horizontal).
  2. V. STAT magnet, align the colored dots in the center of the screen (vertical mixing).
    If the H. STAT control range is insufficient, adjust in the process of information
    vertically with magnet V. STAT. Adjust the tilt by mixing
    V. STAT magnet or by his "discovery" or "closing"


[ندعوك للتسجيل في المنتدى أو التعريف بنفسك لمعاينة هذه الصورة]

Figure 2

  1. If the red and blue dots are not compatible with the green, move the magnet
    Navy (a) to adjust the static data on the horizontal.
  2. Turn the magnet Navy (c) to adjust the static mixing
    vertically.
  3. In any case, repeat the adjustment of the beam hitting the target.


Dynamic reduction of radiation

  1. Loosen the screw the OS.
  2. Remove insert the OS.
  3. Move the OS (see Figure)
  4. Tighten the lock screw the OS.
  5. Insert Insert the OS.


[ندعوك للتسجيل في المنتدى أو التعريف بنفسك لمعاينة هذه الصورة]

Fig.3

Reduction in the corners of the screen
If unreconciled to the corners of the screen attached to a CRT glass bulb to the corresponding
diagonally under the deflection strip of permalloy.

Accelerating voltage, black level, white balance,
Subcolors and subyarkost


Accelerating voltage

  1. Apply the input signal is black field.
  2. In service mode, enter "Test" "Test" and 38
  3. Adjust RV703 (BE-4) or RV701 (BE-4A), yet appears on the screen image
    Down Arrow
  4. Adjust RV703 (BE-4) or RV701 (BE-4A), while "Down Arrow"
    just disappear.
  5. Press the TV button on the remote control to store data.


Black Level

  1. Apply the input signal containing a small area of ​​100% white on black
    background.
  2. Connect the oscilloscope to pin 10 (R OUT) the jumper block on the board J701
    S.
  3. Set the image to the maximum with "Test" "Test"
    and 01.
  4. Sign in service mode (menu, Adjust).
  5. Use [Blue]
    and [Green] select
    in the menu "RED HWB".
  6. Use [Red]
    and [Yellow] on the remote control to adjust,
    to the black level was 85B.


White Balance

  1. Apply the input signal is a white field.
  2. Adjust the color and brightness to a standard level.
  3. Adjust the "GREEN HWB" and "BLUE HWB" so that
    White balance was optimal.


Adjusting Subcolors

  1. Apply the input signal colors are in PAL.
  2. Connect the oscilloscope to pin 8 (OUT) the jumper block on the board J701
    S.
  3. In service mode, enter "Test" "Test" and 22
  4. Use [Red]
    and [Yellow] on the remote control to adjust until
    shape does not coincide with the figure 4.


[ندعوك للتسجيل في المنتدى أو التعريف بنفسك لمعاينة هذه الصورة]

Figure 4
If the TV is SECAM, repeat the adjustment with the signal SECAM.

Adjusting subyarkosti

  1. Apply the input signal grayscale.
  2. In service mode, enter "Test" "Test" and 23.
  3. Use [Red] and
    [Yellow] on the remote control to adjust until
    level grayscale 0 (cutoff level) will not soon see on the screen.


Focusing

  1. Take the television signal.
  2. Set the parameters for the image.
  3. Adjust the focus knob, which is on TDKS to the center
    focusing screen was normal. If you focus only the central region
    appears on the screen purple circle. In this case, adjust so that
    Fullscreen focused equally optimal.


The entrance to the service mode

  1. Turn the power on and enter the mode of "Stand-by".
  2. Push Button [On screen display], [5],
    [Volume +], [TV] on the remote. In the right
    corner of the screen will show the TT. Other information about the state of
    will also be on the screen.
  3. To call the menu screen, press [Menu] on the remote. (See
    Fig. 5)
  4. Press [Blue] ((Next) or [
    Green]
    (Previous) to select from the table position with the designation
    adjustment.
  5. Press [Yellow] (+) Or [
    Red]
    ((-) To adjust.
  6. Turn off the power to shut down the service mode.


[ندعوك للتسجيل في المنتدى أو التعريف بنفسك لمعاينة هذه الصورة]

Fig.5

The range of possible adjustments OSD.

Table 1



Controlled parameter


Value


The range of values
16:9 OFF (screen format)

Chosen


ON / OFF
System (Standard audio)

BG-L, BG-DK, UK
(UK), Eire
(Ireland), BG
Text (Teletext mode)

EAST / WEST / OFF
AGC (AGC)

Regulated


00-63
PLL (PLL)
B & W Delay (delay yarkostnogosignala)
Ver Size (vertical size)
Ver Breath (curvature of vertical)

00
Par.Amp (amplitude of the parabola)
Par.Tilt (slope of the parabola)

32
V. Linear (linear vertical)

Regulated
Com.Corr (correction at the corners)

00
V. Cen or EW (centering povertikali)

Regulated
V. Position (vertical position)

42
H. Centre (centering on
Horizontal)


Regulated
Blue HWB
Green HWB
Red HWB



Log in testing mode

In testing mode you can enter by double-clicking [Test]. On
screen will display OSD "TT-". features described below are caused by successive
pressing the two buttons tsiframi.Dlya exit TT, double-click [
0 ]
Or [Test]Or [TV]Or switch the TV to "Stand-by
.

Table 2

00 Disable TT
01 Setting a maximum level of image
02 Installation-level pictures on a minimum
03 Setting the value to 35%
04 Setting the value to 50%
05 Setting the value to 65%
06 Setting the value to 80%
07 Training conditions (picture and brightness maximum)
08 The condition of acceptance (analog values ​​are reset to the original set
in manufacturing, selected program 1 mode, the TT is switched off, set
volume 35%)
09 Bachelorhood
10 No function
11 Bachelorhood
12 Shift of the test images (scattered / Disable)
13 Select field ODD / EVEN (odd / even) for noninterlaced Teletext.
14 Selecting the display interlaced / noninterlaced teleteksta
15 Reading factory defaults from ROM to the nonvolatile memory (non-voltage
memory - NVM)) - read the volume, brightness, picture (Picture),
Hue (Hue), sharpness, color value (Color values) from ROM to the current
values ​​used ("memory of the last inclusion»-Last Power Memory)
16 No function
17 Enable / Disable control the sharpness
18 Enable / Disable control teletext
19 Enable / Disable Control NTSC
20 No function
21 Subkartinka
22 Subtsvetnost (different memory for PAL and SECAM)
23 Subyarkost
24 Sound System BG / L
25 Sound System BG / L
26 Sound System I
27 Sound System I / I
28 Sound system only BG
29 Bachelorhood
30 30 no funktsii.31-32 idler
33 Automatic adjustment of gain control (AGC)
34 Automatic adjustment of loop (PLL) .35-37 idle
38 Log in adjustment mode black level
39 Bachelorhood
41 Reinitialize non-volatile memory (NVM)
42 Bachelorhood
43 Reinitialize geometric ustanovok.44-47 idler
48 Installation of test bytes NVM is set to "44h"
49 Erasing the test bytes NVM
50 No function.

To test modes 41-50, make sure that the TV
installed the program in 1959


Automatic adjustment drive

  1. Apply a sinusoidal input signal with a frequency of 38.9 MHz and at 100
    dB relative to 1 mW at the exit point of IF (IF Out).
  2. Sign in TT mode, and enter the number 34.
  3. Connect the digital voltmeter to the conclusion that 23 chip IC101.
  4. Check a constant level of the automatic fine tuning signal 2.5 V + -0.3 B
  5. On the remote control, press 00.


Adjusting AGC

  1. Take a non-air signal.
  2. Go to the menu and select Adjust AGC.
  3. Press [Yellow] (+) Or [Red
    ]
    ((-) To adjust until the display disappears "Snow" and cross-
    modulation.
  4. Change the received non-terrestrial channel iubedites the correct adjustment.


[ندعوك للتسجيل في المنتدى أو التعريف بنفسك لمعاينة هذه الصورة]

Figure 6

Adjusting the system scans

  1. Sign in service mode.
  2. Press [Blue] ((Next) or [Green
    ]
    (Previous) to select the menu "Adjust" position with the designation
    adjustment.
  3. Click on [Yellow] To enter into
    submenu of adjustment.
  4. Choose and adjust every position to get the desired image
    (Sm.tabl.1)


In analyzer
Switching to the identification of errors chassis BE-4 (BE-4A) occurs in one of
two cases:

  1. Busy bus.
  2. Device does not respond to commands.

In the case of one of these situations, the program will try, first, to release
bus if it is busy (in case of failure of this will be reported to the continuous blinking
LED) and then connect each device to be relevant to
check them out at defektnost.Esli found defective unit, its number will be
shown on a series of flashes Side (transcript sm.tabl.3), thus reported
of non-fatal errors. If you found a fatal error, the receiver will simply remain
in the same condition it was in when the error occurred, if the same error
not fatal, the receiver will attempt to continue.

Table 3



Number of outbreaks


Value


2
IC301 did not confirm the transfer of I2C, memory NWM in order.


3
IC301 is faulty flags


4
IC301 - no reverse line scan


5
IC301 - stack overflow


6
Protecting the voltage / current (pin 52) - high level


7
IC002 did not confirm the transfer of I2C, IC301 in order


8
IC002 and IC301-no confirmation I2C


9
SDA SCL IC001, CN001
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مُساهمةموضوع: رد: مراجع ودوائر وأعطال و شرح صيانة -CRT-LCD -plasma   الجمعة أبريل 22, 2011 2:39 am


Chassis Nokia Eurostereo 2B-F


Anode voltage <= 28kV. To ensure Ustr = 145V (110 ° MININECK),
150 V (110 °), 130V (90 °) with a minimum current of the beam. Adjustment - R796,
focus R540.

To enter the service mode

[ -/-- ], [Menu], Then [ [ندعوك للتسجيل في المنتدى أو التعريف بنفسك لمعاينة هذه الصورة]
]
on the TV for 1 sec.
[Step + -] - Switching on the gauge to the gauge;
[Volume + -] - Change the value;
[ ] (Progr) - [Memory]Or [
red]
button in the menu.
[Standby] - Exit the service mode.

Table 1

OSD


Function


Display


Note


0 (V. AMP)


Vertical dimension


00


OSD-On Screen Display. Set OSD 0 ... 13 in the test
FUBK picture or similar. See note. 1


1 (V. LIN)


Vertical linearity


01


2 (S. COR)


S - Correction


02


3 (V. POS)


Vertical Alignment


03


4 (H. POS)


Centering Horizontally


04


-

5 (H. AMPI) Horizontal Size
05


-

6 (P. TILT) Keystone
06


-

7 (P. AMP) Correction pads
07


-

8 (P. CORR) Correction on the corner
08


-

9 (G) Black Level
-

See note. 2
10 (R) Black Level
-


-

11 (B) Black Level
-


-

12 (V. BRE) Stabilization of image size
12

See note. 3
13 (LUM.DEL) Time delay luminance signal
13


-

14 (AUDIO) Crosstalk Audio
14

See note. 4


After replacing the EEPROM set the auxiliary
bytes.


Table 2

OSD


Function


Display


Note

15 (OPBYT!) Auxiliary byte 1
1


[ندعوك للتسجيل في المنتدى أو التعريف بنفسك لمعاينة هذه الصورة]

16 (OPBYT 2) Auxiliary byte 1
2

17 (OPBYT 3) Auxiliary byte 1
3

1918 (PR 1.OCK) Lock byte program
18

1919 (RESERVE) Reserve bytes
19

Each bit of 0-8 placed in correspondence with a weighting factor (grade 2) from
1 to 128. The sum of weights for a bit set to 1 by the value
OSD.

Standard menu
(For example, SDA 3526)

Table 3

Subsidiary B


Bit


Factory setting


OSD


Appointment of bits


Note


1


0


-


1


0 - Tuner Samsung, 1 - Teletinken


Inspect the replacement tuner


1


-


2

1 - Tuner Samsung, 0 - Teletinken

2


0


4

0-7-segment. display is off, 1-inc.
-


3


1


8

0-AFC is off, 1-inc.
-


4


0


16

0-NTSC 4.43 Should be 0

5


1


32

0 ext. tsvetoorazn. Signal. Off.
1-inc
0 - in some models

6


1


64

CTI 0-off, 1-on
-


7


0


128

0 Bank Holiday (See note. 5)

2


0


0


1

0-FM/MSP analog. mouth NICAM 1 = FM
-


1


0


2

0-Coobschen FLOF off, 1-inc.
-


2


0


4

0-Czech VT off. In some models

3


0


8

0-chip 1-chip VT2 VT1 In some models

4


1


16

0-timer auto power off, 1-on
-


5


0


32

0-monitoring of the keyboard, off, 1-on
-


6


1


64

0-const vert Time & uS, 1-24uS
-


7


0


128

0-range adjustable volume standards, the 1-reduced
at 10dB

-


3




0


1


1

0-bit evaluation NICAM-C4 off, 1-on See note. 6

1


0


2

0-start off the register, 1-inc See note. 7

2


0


4

0-picture TV off with the help of [Prog]
OFF, 1 ON

-


3


0


8

0-OSD display audio off, 1-on
-


4


0


16

0-analog switch U to 8 pin SCART,
lock switch to AV1 off, 1-inc.

-


5


0


32

0-external SECAM off, 1-on
-


6


0


64

0-open-loop PLL c off. VT, 1-inc Module for VT 5854 40 11 establishment 1

7


0


128

0-OSD volume off, 1-on
-




Setup for TV Mouse
(Eg, SDA 3546)

Table 4

Subsidiary B


Bit


Factory setting


OSD


Appointment of bits


Note


1


0


-


1


0 - Tuner Samsung, 1 - Teletinken


Inspect the replacement tuner


1


-


2

1 - Tuner Samsung, 0 - Teletinken

2


0


4

0 - non-working
-


3


1


8

0
-


4


0


16

0-NTSC 4.43 Should be 0

5


1


32

0 ext. tsvetoorazn. Signal. Off. 1-inc 0 - in some models

6


1


64

CTI 0-off, 1-on
-


7


0


128

0 Bank Holiday (See note. 5)

2


0


0


1

0-FM/MSP analog. mouth NICAM 1 = FM
-


1


0


2

0-Coobschen FLOF off, 1-inc.
-


2


0


4

0-Czech VT off. In some models

3


0


8

0-chip 1-chip VT2 VT1 In some models

4


1


16

0-timer auto power off, 1-on
-


5


0


32

0
-


6


1


64

0-const vert Time & uS, 1-24uS
-


7


0


128

0-range adjustable volume standards, the 1-reduced
at 10dB

-


3




0


1


1

0-bit evaluation NICAM-C4 off, 1-on
-


1


0


2

0-start off the register, 1-inc
-


2


0


4

0
-


3


0


8

0
-


4


0


16

0-analog switch U to 8 pin SCART,
lock switch to AV1 off, 1-inc.

-


5


0


32

0-external SECAM off, 1-on
-


6


0


64

0-open-loop PLL c off. VT, 1-inc Module for VT 5854 40 11 establishment 1

7


0


128

0-shift NTSC off, 1-on
-



Installing the Option Bytes

Table 5



Tools


OSD


Note


1.0

Enter into service by pressing [Step] get 2
-


Bit 3 must be involved


1.1

Press [ 3 ]

1.2

Press [•] - [Memory]Or [
red]
button in the menu, then [Standby]. Values ​​remembered

2.0

Get OPRYTE 1. Set 121
121


for Telefinken, 122 - to Salcomptiner


2.1

[Step +] to go to OPBYTE 2

3.0

OPBYTE 2. Set 088
088


-


3.1

[Step +] to go to OPBYTE 3

4.0

OPBYTE 3. Set 001
-


-

4.1 [Step +] to move to PR LOCK

5.0

PR LOCK
000


-


6.0

RESERVE
000


-


7.0

Remember me (see A.1)
-


-



Approximate values ​​of the OSD

Table 6

-


OSD 90 ° (55cm)


OSD 110 ° (63.71cm)


0 (V. AMP)


005


031


1 (V. LIN)


016


016


2 (S. COR)


020


020


3 (V. POS)


031


017


4 (H. POS)


041


040

5 (H. AMPI)
036


022

6 (P. TILT)
000


020

7 (P. AMP)
000


042

8 (P. CORR)
000


044

9 (G)
052


052

10 (R)
052


052

11 (B)
052


052

12 (V. BRE)
000


000

13 (LUM.DEL)
001


001

14 (AUDIO)
025


032



NOTE: Applies only
for pure EEPROM.


  1. Remembering the language of the user.
    Press 4 * [Menu], [Blue] button
    1 times, and then select the desired language using the button on channel 1 - 9.
    To install a working panel TV Mouse/ES3: On the remote press both buttons
    - [Menu] and [Blue] , Click
    [ندعوك للتسجيل في المنتدى أو التعريف بنفسك لمعاينة هذه الصورة]
    2 times, click [ندعوك للتسجيل في المنتدى أو التعريف بنفسك لمعاينة هذه الصورة]
    , Then select the desired language using the button on channel 1 - 9.
  2. Remembering the color standard and the audio in memory.
    Press 4 * [Menu], [Blue] button
    1 times and [Red] 1 times, then set
    standards. Remember me [Blue] button.
    Repeat for each channel.
    To install a working panel TV Mouse/ES3: On the remote press both buttons
    - [Menu] and [Blue] , Click
    [ندعوك للتسجيل في المنتدى أو التعريف بنفسك لمعاينة هذه الصورة],
    [ندعوك للتسجيل في المنتدى أو التعريف بنفسك لمعاينة هذه الصورة]
    or [ندعوك للتسجيل في المنتدى أو التعريف بنفسك لمعاينة هذه الصورة]
    (Depending on the standard), remember [Red
    ]
    button.


Table Display troubleshooting

Table 7

Error


LED for the sound I


Cvetodiod for Sound II


SAT LED


SAT R LED

Colour IV (Chroma IV)
*


-


-


-

Stereo AF
-


*


-


-

Tuner PLL
-


-


*


-

VT
*


-


*


-

Nicam
-


*


*


-

No KIOH
-


-


-


*

Bus 12C
*


-


-


*

EEPROM
-


-


*


*

Radio / Satellite
*


-


*


*




  • If an error is detected in the MS Chroma (IC 820) or Vertical, TV
    switch to the Stand-by and the corresponding LEDs will flash. Similarly,
    at too high current beam.
  • If an error is detected in the EEPROM or bus 12C, the corresponding LEDs
    blinking, TV switch to Stand-by (without the display "-")
  • if the satellite, radio or TV are not connected, the device will no
    errors.


Eurostereo Chassis 2B-F (90 °)
Eurostereo Chassis 2B-F (110 ° FST 28kV)


Table 8
IC303 / 304 HEF4053BP IC910 TDA4565V2
IC340 MC44131-D 14J IC920 MC44140P
IC350 TDA2616A IC1420 SDA3526 2K prog
IC380 MC1458CP1 IC1420 SDA3546 4K prog
IC401 TDA8170 IC1430 MC3464PS
IC710 TEA2164G IC1440 SL-main 2R01
IC721 L78S05 C-DL60280 IC1440 NES 3 C R003
IC723 L78S12 IC1440 NES 3 C R04
IC770 MC78L05ALP IC1440 NES 4 -1 R01
IC780 TEA5170 IC1440 NES 4 - 2 R01
IC820 44000D20
-


-



Displays control panel in the service mode.

  1. LED for audio I - Recognition PAL
  2. LED indicator for sound II - Recognition SECAM
  3. SAT LED - the maximum beam current, the lower limit
  4. SAT R LED - the maximum beam current, the upper limit


Paragraphs 3 and 4, not all devices.



Note:

  1. OSD 1 ... 3 must be installed.
  2. Set the value of 052 for OSD 9-11, R540 in the average position, brightness
    nominal, resistor R540 black level on the cathodes exhibit 168V. Adjusting
    OSD 9-11, set the white balance in the black.
  3. Stabilization of the size. Set the size at maximum brightness and contrast,
    then take away them to a minimum. If the scan periodically turned off, repeat
    OSD 12.
  4. Connect the stereo signal of 1 kHz. Left channel without modulation. Oscilloscope - to
    pin 3 SCART. Set the minimum value.
  5. Set all non-working bits to 0
  6. Bit indicates whether the same sound for NICAM and FM, and whether you want automatic
    switching.
  7. Byte block of programs. Decimal value (which appears on the screen) indicates
    the latter is blocked by a program number (1-59), 0 - no position is not blocked.

    EXAMPLE: to block the first 26 rooms, set 26, or digital
    bit1 keys, bit3 and bit4.

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مُساهمةموضوع: رد: مراجع ودوائر وأعطال و شرح صيانة -CRT-LCD -plasma   الجمعة أبريل 22, 2011 2:49 am

Color TV PANASONIC chassis MD1

Microcontroller



On the chassis MD1 used microcontroller SDA30C164 (IC
IC1101). The central element of the microprocessor is a circuit CPU8051
and built-in memory RAM (random-access memory), which is used
as working memory.
These two blocks of RAM memory have a capacity of 256 bytes and 2048 bytes. Software
required to operate the microprocessor is stored in ROM (ROM - read-only memory
unit) capacity 2Mbayt with vibrational frequencies of detectable channels
and address of the integrated circuit (IC).
EAROM (electrically programmable ROM) on the integrated circuit IC1103

Planning data channels, the configuration data (ADJ)
EAROM Integrated Circuit IC3503
Aspect (Aspect - a property on which a group of data is combined into one
Block) data (fixed) text (TEXT) data

• Input from the keyboard (console) (KEY IN), a stem 50 integral
scheme IC1101

Table 1
Voltage (V) Keyboard Input


0.000 - 0.625
CH DOWN (decrease in channel number)


0.625 - 1.250
CH UP (increase in channel number)


1.250 - 1.875
VOLUVE DOWN (decrease volume)


1.875 - 2.500
VOLUME UP (increase volume)


2.500 - 3.125
TV / AV (TV / AV)


3.125 - 3750
PRESET Preset


3.750 - 4.375
DISPLAY (Display)


4.375 - 5.000
-
• Protection (PROTECT), an integrated circuit pin 51 IC1101

Table 2
Voltage (V) Type I emergency


0.000 - 1.250
NORMAL (normal)


1.250 - 2.500
Hold Down (default setting)


2.500 - 3.750
Shout down (stop)


3.750 - 5.000
Abnormal voltage


IC1101

Table 3
Number of legs Input / Output (I / O) - Function
44 0 SCL0 IIC bus clock Clock0 for the integral
scheme IC3501 (TEXT)
43 0 SDA0 IIC bus data for the integrated circuit IC3501 (TEXT)
42 0 IICAN
23 0 SCL1 IIC bus clock Clock1
22 0 SDA1 IIC bus data Data1
21 0 SCL2 IIC Bus Clock Clock2 for the integral
IC3501 and other schemes
20 0 SDA2 IIC bus data Data2 for an integrated circuit IC3501
and other
19 0 SCL3 IIC bus clock Clock3 for the integral
IC1103 and other schemes
18 0 SDA3 IIC bus data Data3 for an integrated circuit IC1103
and other
1-3. 7. 46. 47. 56-68 - A0-A18 Address bus for an integrated circuit IC1102 (EPROM -
Erasable programmir.PZU)
8-15 - D0-D7 Data bus for an integrated circuit IC1102 (EPROM)
26-27 - XTAL Input / output of inverting amplifier vibration generator
28 0 Reset L (low): omission; H (high) normal
24 - VDD Supply voltage
25 - VSS Land
6 - - VAREF Analog reference voltage
4 - - VAGND Analog Ground
5 - PSEN Program storage device operates
16 0 SBT Serial bus DSP (Digital Sound Processor
signals)
17 0 SBD Serial bus DSP (Digital Sound Processor
signals)
29 0 DSPEN DSP processor operates
31 0 S. DEF. L (low): Normal; H (high): Violation of sound
33 0 SIF1 L (low): 4.5 M, 5.5 M c / H (high): 6.0, 6.5 M Hz
34 0 SIF2 L (low): 4.5 M, 6.0 M c / H (high): 5.5, 6.5 M Hz
41 1 S. AI Audio input AI
30 0 RFAGC1 Voltage AGC (Auto Gain Control)
0-5V for the main tuner
48 1 AFC1 Voltage AFC (Automatic Frequency Control)
for the main picture
49 1 AFC2 AFC voltage for additional images
32 0 M. DEF. L (low): Average H (high): Flag images
35 - S. SYSC Search and synchronization (SYNC)
37 1 SYNC1 Synchronization signal SYNC for the primary image.
H (high): no signal SYNC
38 1 SYNC2 Synchronization signal SYNC for additional images.
H (high): no signal SYNC
50 1 KEY Input from the panel keypad (KEY)
51 1 PRTCT Terms of supply
52 0 RELAY Relay. L (low): ON (enabled), H (high): OFF (off)
53 0 LED LED. L (low): Standby, H (high):
ON (enabled)
54 0 RST.2 Reset the device. L (low): ON (enabled), H (high):
OFF (off)
55 0 H. STP. Stop the horizontal sweep. L (low): ON (enabled);
H (high): OFF (off)
39 1 RMCN Input the remote control



IC IC1002 (expansion EXT.1)

Table 3
Leg Function Notes
1 TV / AV L (low): AV (audio video) H (high): TV (television)
2 - -
3 C. SP VOL The volume of the center speaker
4 - -
5 DAF PHASE
6 DSP ON / OFF L (low): OFF (off) H (high): ON (enabled)
7 50/60 L (low): 60 H (high): 50
8 GND -
9 V / G. ON / OFF L (low): ON (on) H (high): OFF (off)
VCR / GAME (VCR / play)
10 4:3/16:9 L (low): 16:9 H (high): 4:3 Aspect Ratio
11 SAD0 Slave address
12 SAD1 Slave address
13 SAD2 Slave address
14 SDA1 IIC bus data Data1
15 SCL1 IIC bus clock Clock1
16 9V -

IC IC1001 (extension EXT.2)

Table 4
Leg Function Notes
1 SUB S1 L (low): 4.5 M, 5.5 MHz, H (high): 6.0, 6.5 MHz
2 SUB S2 L (low): 4.5 M, 6.0 MHz, H (high): 5.5, 6.5 MHz
3 SUB CONT Contrast additional images
4 - -
5 SUB VOL Stress in volume 0.5 - 9.0 in
6 RF AGC2 Voltage AGC (Auto Gain Control)
tuner additional images
7 SUB WOOFER (ON / OFF) switch on / off device AERO 4D
8 GND -
9 L. P. SW. L (low): Switch M / W disabled (OFF), POP (memory
magazine-type) H (high): TWL, TWS
10 S. H. MUTE Muting headphone additional images
11 SAD0 Slave address
12 SAD1 Slave address
13 SAD2 Slave address
14 SDA1 IIC bus data Data1
15 SCL1 IIC Bus Clock Clock
16 9V -

Intermediate frequency (IF)


Intermediate frequency video signal (VIF)



Signal Processing VIF (picture intermediate frequency) signal
VIF, coming from the tuner is on the two routes. One, designed for
Signal Processing SIF (intermediate frequency audio signal) passes through
transistor Q104, and the other, is designed to handle signals VIF (intermediate
frequency videoosignala), passes through the transistor Q102.

Intermediate frequency amplifier (IF AMP) on the transistor Q102 is formed to
compensation for loss of input signal in the filter H101.
Signal VIF (picture intermediate frequency) filter is applied to the H101, which
generates the required bandwidth.
With the filter output signal H101 by connecting chains of alternating current
fed through capacitors S112 and S114 on the legs of 4 and 5 of the integrated circuit IC101.
These are inputs to the first gain stage VIF (video intermediate frequency).

After amplification, the signal passes to the cascade detector video signal, then through
scheme AFC (Automatic Frequency Control) tuner and a scheme for APC (Automatic
phase adjustment) for the detection and reference signal.

After detecting the signal is output to the leg 18 and passes through the circuit
notch SIF (intermediate frequency audio signal) to remove the component
SIF (intermediate frequency audio signal). Voltage AGC (automatic adjustment
gain), gain level control circuits VIF AMP (amplifier picture
intermediate frequency), smoothed by a capacitor S113, the connected
to pin 8 of integrated circuit IC101.
AGC output voltage with three legs of the integrated circuit is applied to the scheme of RF-AMP
(High-frequency amplifier), tuner and manages the gain level.
This video is output from the leg 18 of the integrated circuit IC101 and enters
for each scheme notch SIF (intermediate frequency audio signal).
Output signals from each of the aforementioned notch filters connected
to the corresponding input pin, which are switched according to each
TV color systems. The signal is output with 20 feet of the integral
circuits IC201 and sent to the circuit switching AV (audio video).
In accordance with the specific combination of input voltage internal logical
scheme organized by the circuit switching notch filters SIF (intermediate
audio frequency).
SIF switching control signals are issued with a scheme MPU (microprocessor unit).


Table 1
f (Mhz) Leg 12 Leg 14


4,5
L (low) L (low)


5,5
L (low) H (high)


6,0
H (high) L (low)


6,5
H (high) H (high)


Intermediate frequency audio signal (SIF)




Signal Processing SIF (audio intermediate frequency) SAW (SAW) - Filter
(Filter surface acoustic waves) H102 provides a selection signal
VIF (video intermediate frequency) with a very sharp selectivity with respect
adjacent channel interference.
Detector SIF (intermediate frequency audio signal) is used to detect
frequency modulated (FM) signal. This intermediate frequency signal having
constant amplitude, is first converted into a proportional voltage, which
changes both in frequency and amplitude. Thus, detection of frequency-
modulated (FM) signal does not react to changes in amplitude.
In order to provide better sound reproduction, with
voltage controlled oscillator (VCO) is formed by feedback frequency-modulated
(FM) signal.
Sound component (SIF) is obtained from the video output after passing
through a bandpass filter BPF. This constraint limits the amplitude of the sound
signal with information about the beats coming from the video detector,
and not the same degree of inclusion (implication) on the cascade of RF (high frequency)
and IF (intermediate frequency).
To attenuate high frequency sound is applied predistortion correction circuit,
which serves to compensate for the preemphasis arising on the transmitting side.
This restores uniform through-frequency response
with improved signal-to-noise ratio.
Then the sound frequency-modulated (FM) signal with an amplifier-limiter
and a detector (FM), is converted into a multiplex an audio signal.


Switch SIF (intermediate frequency audio)
SIF output signal with 13 feet of the integrated circuit IC101 through the filter BPF (bandpass
filter) (filter X203-X205) is fed to integrated circuit IC201.
This input signal is converted into a signal frequency of 6.0 MHz and fed to a switching
part of the scheme. Switching this signal SIF is carried by the signal
Switching SIF (intermediate frequency audio signal), which comes from the output
microprocessor MPU to the legs 12 and 14 of the integrated circuit IC201. SIF signal arrives
on the output legs 9, then passes through a bandpass filter BPF (H202) and served
on the leg 11 of the integrated circuit IC101.
In the integrated circuit IC201, in addition to the normal switching operations, there
ability to convert any frequency SIF, regardless of the frequency
SIF, the signal frequency of 6.0 MHz. In the past, this scheme used four filters
detector SIF, which was carried out in accordance with the switch size
frequency of SIF (intermediate frequency audio signal). However, in this system,
through frequency conversion, using only one filter for the frequency
6.0 MHz. So, now no longer required in the above switching
and thereby reached the rationalization scheme.

Table 2
f (Mhz)
Leg 12 Leg 14


4,5
L (low) L (low)


5,5
L (low) H (high)


6,0
H (high) L (low)


6,5
H (high) H (high)
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Color TV PANASONIC chassis MD1


Intermediate frequency (IF)


Intermediate frequency video signal (VIF)



Signal Processing VIF (picture intermediate frequency) signal
VIF, coming from the tuner is on the two routes. One, designed for
Signal Processing SIF (intermediate frequency audio signal) passes through
transistor Q104, and the other, is designed to handle signals VIF (intermediate
frequency videoosignala), passes through the transistor Q102.

Intermediate frequency amplifier (IF AMP) on the transistor Q102 is formed to
compensation for loss of input signal in the filter H101.
Signal VIF (picture intermediate frequency) filter is applied to the H101, which
generates the required bandwidth.
With the filter output signal H101 by connecting chains of alternating current
fed through capacitors S112 and S114 on the legs of 4 and 5 of the integrated circuit IC101.
These are inputs to the first gain stage VIF (video intermediate frequency).

After amplification, the signal passes to the cascade detector video signal, then through
scheme AFC (Automatic Frequency Control) tuner and a scheme for APC (Automatic
phase adjustment) for the detection and reference signal.

After detecting the signal is output to the leg 18 and passes through the circuit
notch SIF (intermediate frequency audio signal) to remove the component
SIF (intermediate frequency audio signal). Voltage AGC (automatic adjustment
gain), gain level control circuits VIF AMP (amplifier picture
intermediate frequency), smoothed by a capacitor S113, the connected
to pin 8 of integrated circuit IC101.
AGC output voltage with three legs of the integrated circuit is applied to the scheme of RF-AMP
(High-frequency amplifier), tuner and manages the gain level.
This video is output from the leg 18 of the integrated circuit IC101 and enters
for each scheme notch SIF (intermediate frequency audio signal).
Output signals from each of the aforementioned notch filters connected
to the corresponding input pin, which are switched according to each
TV color systems. The signal is output with 20 feet of the integral
circuits IC201 and sent to the circuit switching AV (audio video).
In accordance with the specific combination of input voltage internal logical
scheme organized by the circuit switching notch filters SIF (intermediate
audio frequency).
SIF switching control signals are issued with a scheme MPU (microprocessor unit).


Table 1
f (Mhz) Leg 12 Leg 14


4,5
L (low) L (low)


5,5
L (low) H (high)


6,0
H (high) L (low)


6,5
H (high) H (high)


Intermediate frequency audio signal (SIF)




Signal Processing SIF (audio intermediate frequency) SAW (SAW) - Filter
(Filter surface acoustic waves) H102 provides a selection signal
VIF (video intermediate frequency) with a very sharp selectivity with respect
adjacent channel interference.
Detector SIF (intermediate frequency audio signal) is used to detect
frequency modulated (FM) signal. This intermediate frequency signal having
constant amplitude, is first converted into a proportional voltage, which
changes both in frequency and amplitude. Thus, detection of frequency-
modulated (FM) signal does not react to changes in amplitude.
In order to provide better sound reproduction, with
voltage controlled oscillator (VCO) is formed by feedback frequency-modulated
(FM) signal.
Sound component (SIF) is obtained from the video output after passing
through a bandpass filter BPF. This constraint limits the amplitude of the sound
signal with information about the beats coming from the video detector,
and not the same degree of inclusion (implication) on the cascade of RF (high frequency)
and IF (intermediate frequency).
To attenuate high frequency sound is applied predistortion correction circuit,
which serves to compensate for the preemphasis arising on the transmitting side.
This restores uniform through-frequency response
with improved signal-to-noise ratio.
Then the sound frequency-modulated (FM) signal with an amplifier-limiter
and a detector (FM), is converted into a multiplex an audio signal.


Switch SIF (intermediate frequency audio)
SIF output signal with 13 feet of the integrated circuit IC101 through the filter BPF (bandpass
filter) (filter X203-X205) is fed to integrated circuit IC201.
This input signal is converted into a signal frequency of 6.0 MHz and fed to a switching
part of the scheme. Switching this signal SIF is carried by the signal
Switching SIF (intermediate frequency audio signal), which comes from the output
microprocessor MPU to the legs 12 and 14 of the integrated circuit IC201. SIF signal arrives
on the output legs 9, then passes through a bandpass filter BPF (H202) and served
on the leg 11 of the integrated circuit IC101.
In the integrated circuit IC201, in addition to the normal switching operations, there
ability to convert any frequency SIF, regardless of the frequency
SIF, the signal frequency of 6.0 MHz. In the past, this scheme used four filters
detector SIF, which was carried out in accordance with the switch size
frequency of SIF (intermediate frequency audio signal). However, in this system,
through frequency conversion, using only one filter for the frequency
6.0 MHz. So, now no longer required in the above switching
and thereby reached the rationalization scheme.

Table 2
f (Mhz)
Leg 12 Leg 14


4,5
L (low) L (low)


5,5
L (low) H (high)


6,0
H (high) L (low)


6,5
H (high) H (high)
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Color TV PANASONIC chassis MD1

Management of AV (audio video)
VIDEO


Video signal from the findings of the tuner AV1, AV2, AV3, AV4 is fed to integrated circuit
IC3001. The relationship between input (INPUT) and OUTPUT (OUTPUT) is set
follows.

Table 1
Input (INPUT) OUTPUT (OUTPUT)
Full TV Video Leg 35 The main image (MAIN)
Leg 42 Embedded image (SUB)
Cable videsignal (S-Video) Leg 37 signal Y (brightness) for the MAIN
(Y and C - brightness and color) Leg 33 signal C (chroma) for the MAIN
Leg 44 Y signal for the SUB
stem 40 Since the signal for the SUB
SOUND


Video signal from the findings of the tuner AV1, AV2, AV3, AV4 is fed to integrated circuit
IC3001. Then, after the choice of using a switch audio
(Audio), the signal is output to the legs 54 and 52 for the main image (MAIN)
and on the legs 59 and 57 for the embedded image (SUB).
Detection signals of cable television (S-Studio)
When you connect the input cable (S-Video) legs 9, 14, 19, 24
(Input signal stalk C-chroma) are opened on the basis of this scheme determines
that introduced the signal S-Video (CCTV). Switch Video
transferred to the side S-Video. If the contact S-Video is not connected, the signals
on the aforementioned legs are mounted on a low level, whereby
determined that the S-Video signal is not received by this switch vhod.Pri
Video is transferred to the side (COMPOSITE) full of television video.
This information is fed to the microprocessor MPU, resulting in the on-screen
displayed input signals ON-SCREEN (TV) or S-Video (cable
television).
Datektirovanie mode S1 (VCR, compact disc, digital compact
CD)

When connected to the contact S-Video, and the output signal is sent from a VCR,
player or CD, then the signal on the legs 5, 10, 15, 20, goes high
level. This information is transmitted to the microprocessor MPU resulting pronged
(Group data) mode is automatically replaced by the regime of full
"FULL" treatment.

VIDEO PROCESSOR GLC (RGB)



VIDEO PROCESSOR GLC (RGB)



Latest integrated circuit in the cascade of video processing
not including the output stage GLC (RGB), is an integrated circuit IC603 - TDA4780.
This is a purely analog module, which was designed by the following
functions.

  • Serves as an input circuit for the chroma signals R - Y, B - Y and the signal
    brightness.
  • Matrix scheme for generating the GLC (RGB) signals from the difference signals.
  • Scheme selection signal to select the desired signal GLC.
  • Managing color saturation, contrast and brightness.
  • The scheme of automatic locking of the beam.
  • Bus interface and control register.

Color difference signals R - Y, B - Y and Y signal after passing through further
processing PCB DG (DG-PCB) through the legs 42, 44, 46 connector A44 back
PCB-E (E-DAM). These signals, which are now signals
double the frequency of 100 Hz, fed to integrated circuit IC603 through the legs
6, 7 and 8 for the latter, not including the output stage GLC (RGB), the processing stage
video. With the input pins 6, 7 and 8, the signals are fed to two series
connected matrix schemes, which are used to restore the green
component and the formation of GLC signals (RGB).
These signals are then fed to the GLC scheme of choice, which receives in addition
through the legs 2, 3 and 4 of the GLC signals from the processor Teletext (Teletext).
On the circuit of choice, depending on the mode of operation affects a high
signal suppression in the channels on legs 1 and 13, or control signal
issued by the microprocessor MPU bus via IIC. GLC signals and a signal Y (luminance)
pass through a scheme of color saturation and fed to a cascade of regulatory
contrast and brightness.
GLC signals are output from the legs 20, 22 and 24 with the maximum value
5.5 signal in the full scope. In order to ensure the independence of the image
from aging pipes, by reconfiguring through output amplifiers. For
This scheme used to estimate the leakage current and the current lock together with a microprocessor
MPU.
Leg 15 is connected with the base row transformer FBT. Through this chain
special circuit built into an integrated circuit, receives information about the value
beam current at the time when it flows through the CRT. If there is an excess
maximum value, then using the corresponding cascade control
included in this scheme is reducing the contrast and brightness.

Signal amplifier GLC (RGB)


GLC signals received from the integrated circuit IC603, located on the printed
card E (E-DAM). Each of the signals fed to the leg 3 IC IC351,
IC352 and IC353. Then each of these signals is amplified and fed to the output
on leg 8 of each of these integrated circuits. The amplified signal is fed to the cathode
CRT.
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Color TV PANASONIC chassis MD1PCB DG




Video Processor (VPC3210A)



Performed on a single chip processor VPC3210 contains high quality
video processor, which is designed for television sets with the format
4:3 and 16:9, Frequency 50/60 Hz and 100/120.
VPC3210 video processor has the following characteristics:




  • All video processing is done entirely in digital form.
  • Adaptive sharing scheme Y / C (luma / chroma), based on grabenchatogo
    Filter 2H (delay in 2H - 2 sweep period).
  • Multistandard color decoder PAL / NTSC / SECAM.
  • Integrated analog-digital converter.
  • Synchronization processing.
  • Horizontal scale.
  • Panomirovaniya function.
  • Clock generator synchronized with the frequency lines.


Analog preprocessor


This unit provides an analog interface for video input and,
basically, converts an analog-digital.
DCO (crystal oscillator clock with digital control).


Digital control quartz oscillator by digital signal processor.
Frequency clock can be adjusted in the range of ± 150 ppm.
Adaptive comb filter
Adaptive comb filter is used for high-end division
"Brightness / color" signals of PAL or NTSC. Comb filter
improves resolution in brightness (bandwidth) and reduces the noise level,
such spurious patterns caused by crosstalk, "color-brightness and
"Brightness-color." This adaptive algorithm can eliminate most
of the above errors without introducing new patterns or parasitic noise.
Color Decoder


This circuit performs the standard luma / chroma separation and multi-standard
demodulating the color signal. In the scheme of demodulating the color signal is used
asynchronous clock generator that allows to unify the architecture
standards for all systems of color television.
Scheme of horizontal scaling


Signal YIUV (brightness / chroma) from the decoder is processed by color
pattern of horizontal scaling. The main image is compressed and subjected to
interpolation on a percentage that is specified in the original data.

Synchronous Processing


Signal is formed of horizontal and vertical sync, which is then
served on weekends legs 14 and 12. Formed signals frequency 13.5 MHz and
27.0 MHz.
IIC bus
Relationship between unit VPC (video processor) and external control by
through the bus IIC. Leg 55 - Data SDA (data channel) Leg 56 - Clock SCL (channel
clock)


MULTI-WINDOW FUNCTIONS


With the help of integrated circuits IC1309 and IC1310 can perform the following functions.


  • Two windows
  • Gated all / part of the gated
  • Embedded image in the main image
  • Additional image outside the main image

Signal Y and UV signals are received from video processor VPC (IC1311) on the legs 120-127
and 112-119, sootvetstvenno.Zatem they are compressed and interpolated across.
Interpolation of these signals in the vertical by using the built-in
memory on the line. After that, with an external integrated circuit memory
on the field, these signals is compressed vertically. And in the end, the above
signal and the main image are mixed and disguised and served on
output.


V-PROCESSOR (Vertical Scan)


General Information


This V-CPU, which is part of UP-converter (with
increasing frequency), was specifically designed to aid in
display with interlaced scanning at a frequency 100/120 Hz to improve the quality
image.
V-processor has features that allow you to work with various
standards (formats) of the signal, for example: 4:1:1 or 4:2:2. This V-Processor
designed for operation in synchronous with the frequency of lines (Line-locked mode).

This ensures consistency in time for the synchronization signals
H / V (horizontal / vertical) is the same as that of the processed signal.

This video, which is also rigidly connected with the frequency of lines (Line-locked),
accompanied by synchronization signals H / V, which are converted to scan
with doubled frequency. This format scanner with double the frequency is the main
characteristic feature of the V-CPU.
In this processor scan signal is converted into a map with twice
frequency sweep. In addition, V-CPU is used to at
using digital signal processing to achieve the zoom (Zoom) pictures
in the vertical direction.
In previous models, the chassis with a frequency of 100 Hz for noise reduction.
In this model, the V-Protsesoore provides signal processing to suppress
interference. For this purpose, a special noise filter. This filter
adapts to the local motion picture. For this purpose, types of motion
divided into 4 categories. Decision made on the basis of three threshold
values ​​that are specified using the software for both luminance
and for color, independently of each other. And finally, the output V-Processor
suppresses the flickering images of large areas associated with the process of alternation
lines, and, moreover, increases the resolution of the active image. To
perform the processing of this type, V-processor is necessary to use a certain
Memory RAM (memory device with random access). Therefore,
RAM memory must have a full interface with the V-CPU. In addition, V-Processor
may have an additional function of freezing the image. This functional
feature is also known as "freeze-frame mode or
still image.
Aggregate data on the functional characteristics



  1. Interlace frequency of 100/120 Hz
  2. Suppression of flicker lines
  3. Interline flicker suppression
  4. The suppression of creep lines
  5. Scaling (stretching) along the vertical
  6. Interference rejection, adaptive with respect to the mean motion
  7. Freeze Frame
  8. Interface based on bus IIC.



FUNCTIONAL DESCRIPTION


Luminance signal, which comes from the output of the integrated circuit IC1309, comes
the input of the V-CPU through the legs 1, 2, 4, 5, 205-208.
While the color signal coming from the integrated circuit IC1309, comes
the input of the V-CPU on the legs 187, 188 and 190-195.
The main functions of V-CPU are as follows.

  • UP - Transformation (with increasing frequency).
  • Vertical panning.
  • Scaling.
  • Interference suppression.
  • Linear interpolation lines.

UP - The transformation is carried out through the following means:

  • Formation of additional fields for mode rotation frequency 100/120
    Hz.
  • Formation of new fields / frames for the implementation of scaling vertically.

Adaptive interference suppression scheme operated bus IIC. For luminance
and color, this scheme implemented with a filter with impulse response
infinite length (IIR filter) with a delay of a frame. To
avoid spurious patterns, used the scheme of interference suppression and
UP-conversion, controlled motion detection scheme based on frame
which works with the signal intensity. Operations in the schemes of interference suppression, detection
motion and the UP-conversion are performed using the memory circuits in the field. On
shown here, the figure shows the structure of V - CPU and main elements
memory. From this block diagram shows that the brightness and color signals are
on some routes, processing, and for each route requires two memory
on the field. Cascades of noise and motion detection process information
speed of incoming signals YUV. A cascade of UP-convert to process
and delivery of information at double speed. For motion detection is required
external memory blocks. These external memory blocks are needed for filtering
data traffic and for traffic flow information on a cascade of UP-conversion.
For communication with the scheme UP-conversion using the second output of the external blocks
memory.
Management by V-Processor via bus IIC. Internal diagram
Control (CTRL) V-processor is used to control external units
memory and other stages within a given integrated circuit.
Circuit Description


V-processor can be partitioned into separate blocks. Those listed below are the blocks
and will be described in this section.

  • Detection of motion (block MD)
  • Interference rejection (block NR)
  • Vertical filter (block VF)
  • Management
  • Output stage
  • Motion detection (MD)

The scheme of motion detection signal intensity, which comes
the input of the V-CPU through the legs 1, 2, 4, 5, and 205-208 with a frequency of 15.625 lines
MHz.
Cascade motion detection has two outputs, signals which are fed
at:

  • Suppression scheme (NR)
  • Vertical filter (VF)

For the detection (determination of the form) of the motion used one line from
current frame and one line from the previous frame. Information previous frame
kept in an external storage device, integrated circuit IC1303.
Required information frame is output through the legs 9, 11-12 V-Processor
and is included in the memory block frame (IC1303) via the leg 6-8. This information is then
protrudes from the integrated circuit memory frame through the legs of 9-11 and returns
back to V-processor and is inserted through the leg back to the 8.6 schema detection
movement. After that, the motion detector uses this information to control
as interference suppression scheme (NR), and the pattern of vertical filter (VF).
Interference rejection (NR)
Cascade suppression is used to reduce distortions in the main image
by averaging the two signals from successive scans, or frames. Such
interference suppression schemes are available in both routes of processing - as the luminance signal,
and chrominance. In order to implement noise suppression require external
memory blocks per frame and a string.
The advantage of the method of interference suppression based on frame compared to the method of suppression
interference on the basis of the field lies in the fact that in the first, thanks to the averaging of the line
X frame A0 and A1 lines x frame in which, as a result, averaged element
images in the same vertical position, remains a complete solution
vertically. While in the method of noise reduction based on the field is
smoothing along the vertical, resulting in a deterioration of resolution.

This is because the line X-1 from 0 and the string X are in different positions
vertically. If the motion detector determines a strong movement in video
the coefficient of interference suppression is set to a lower value on
Compared with those cases. when the motion is not detected at all (eg,
still image). This is because when applying a strong impact
suppression of fast motion video on an effect known
called "comet tail" or "toffee" (smear)
for objects moving across the screen.
Processing of luminance
Luminance signal passes through a cascade of suppression, where the signal is
the scheme of averaging. This served as the delayed signal intensity, which
enters through the input DYIN V-CPU (legs 13-14 and 16-21) and comes with an integral
memory circuits IC1303. In this circuit, this delayed luminance signal is subtracted
of the above are not the delayed signal, which provides lowering
interference. Then, the luminance signal with reduced noise comes from the cascade of suppression
interference, and is output through the V-CPU legs 138-141 and 143-146 (YNROUT),
where it comes from on the integrated circuit blocks of external memory IC1302. From these
memory block luminance signal is introduced back to the V-CPU through 86-98 feet
(VFIN) and falls on the vertical filter (VF).
Processing of chrominance
Interference suppression for color signal in exactly the same as for
considered above, the luminance signal. However. processing route, of course, on the other.
Color signal arrives at the V-CPU through the findings UVIN (leg 187, 188
and 190-195). Hence the color signal is fed to a cascade of noise and goes
the scheme of averaging. Here served as a detainee color signal, which
enters through the input DUVIN (170-173 feet) and comes with an integrated circuit memory
IC1301 and subjected to homogenization with a non-delayed signal chromaticity. This provides
significant reduction in the level of interference in a signal color. Then the color signal
low level of interference comes from the cascade of noise and served on
Output V-CPU through outputs UVNROUT (124-127 feet, 128, 129, 132, 133),
where it comes from on the integrated circuit blocks of external memory IC1301 and IC1302.

Vertical filter (VF)
In addition, the motion detector applied to the output signal information on the vertical
filter, which is used to perform linear interpolation line and the suppression
flickering lines. This vertical filter is a key element of the V-CPU,
because it is used for linear interpolation of the line, the result is
depends on the information received from the motion detector. To perform the interpolation
requires the following signals:
Luminance

  • VFIN, legs 81-84, 86-93, coming from the integrated circuit IC1302
  • DLYIN, with 148-156 feet coming from the integrated circuit IC1302
  • YVFIN, legs 64-76, coming from the integrated circuit IC303.

Output terminals DLYOUT (leg 22-25, 28-31) share information with the V-CPU
on an integrated circuit memory IC1303. Chrominance signal

  • UVVFIN, legs 81-84, coming from the integrated circuit IC1721.
  • DUVIN, stem 174-175/177-178, coming from the integrated circuit IC1302
  • DUVIN, 115-118 feet, coming from the integrated circuit IC1724.

Reading of information from the above-mentioned integrated circuit memory is
double speed. That is, the signals are read at the entrance with a frequency of 16
kc, read the output with a frequency of 32 kHz. As a result, this translates into
that each field (half frame) is reproduced on the screen twice. Frequency
personnel increased from 50 to 100 Hz. As a result, large areas of flicker
image inherent in a television receiver with a frequency of 50 Hz decreases.
As a byproduct of this block of memory it should be noted, also,
the possibility of obtaining a still image. This result is achieved
using the control channel, which consists of the legs 105, 161, 196, included
series with memory blocks on a field that is used to preostanovit
overwrite the old image data and information movement. In the freezing
images can still use the zoom mode and vertical
panaromirovaniya mode. This allows you to enlarge a specific area
screen.
Blocks of memory on the field and the line
From the above block diagram shows that there are three integrated circuit memory.
This integrated circuit memory of Siemens brand SDA9251 and SDA9253, which
are dynamic blocks of memory with serial access designed
for use in television (TV-SAM).
Integrated circuits such as SDA is a dynamic memory blocks serial
access with built-in ports, which are intended for processing
video with high speed data transmission. They are organized like
read: 212 series 64 speakers and 16 sets of 4 bits. This allows us to keep
in memory of 4-bit planes of television (TV) fields (NTSC, PAL, SECAM) with
standard or studio (wired) quality. Schema standard TV-SAM apply
in blocks of memory on the field and on line. IC IC1303, which is served
signal DL-YOUT, uses this signal to generate a signal DYIN.
This latter signal is used to detect motion. Integral
circuit memory IC1303, which operates at clock pulses, accounting for half
from the system clock as the input and output, is used
in order to obtain the necessary information movement.


BLOCK DFU (Block digital features)



To improve the quality of the image block is used FJB007, which performs
this problem by improving the quality of signals color, black and white. Except
order to enhance the contrast, here we use the expansion level
black.

  • Input for digital AI

    Signal Y (brightness) / leg 37, 39-42, 44, 45, 63
    Signal UV (chroma) / 54-59 feet, 52
  • Log in to automatically format

    Signal Y (brightness) / 75-82 feet
    Signal UV (chroma) / 65-72 feet

Adaptive scheme YNR (suppression luminance signal)
This scheme is quantitatively detects (determines) the noise level during the blanking
Vertical refresh the image signal (YIN). Then, the period in which
can be made removing interference is automatically changed in accordance
with diagnosed by detecting the level of interference. Scheme AI (Artificial Intelligence
- Artificial Intelligence) This scheme allows you to make a more natural improvement
in image quality in the scheme scales smaller than the standard.

Sharpness of the vertical
In this scheme, there are two blocks of memory on the line for the luminance signal and 1 block
memory (latency 1H) for chroma. Before the advent of the image
required to produce two difference calculations involving the three pieces of information.
In the received signal, in addition to the original signal, this scheme establishes
limitations in the perpendicular direction.
Sharpness of the horizontal
The same as in the scheme AN5342
High-frequency correction (emphasis circuits) In this scheme uses
information Y / C (luma / chroma), obtained after treatment with two screens.
This scheme checks the line and the image detail in the signal. Since
of review (audit) of the line, then running the scheme VM (velocity modulation).
It creates an image that is hard to see at the boundary of the 2 screens.
Therefore, this scheme generates momentum which suspends the scan line
for some additional positions in the horizontal direction, corresponding
the time when such decision was taken. This scheme, in accordance with
control pulse, checks the boundary region.
CTI (chroma noise suppression)
Checks the line for the signal UV (chroma)
CRI (Improved resolution in color)
This circuit receives the input signal to UV (chroma) and regulates the action at the level of
Unit test line in the part that refers to the fluctuations with large
amplitude.
VM (velocity modulation)
That part of the scheme, in which the signal is formed VM, produces the output signal
obtained by calculating the 1-st derivative of the luminance signal, as
signal VM.
Automatic formatting (Samoformatirovanie)
This circuit detects the position of a framework character image at the top
part of the image, position the bottom of the image and the position of credits
in these images. The scheme transmits this information via the IIC bus to the microprocessor
MPU.
الرجوع الى أعلى الصفحة اذهب الى الأسفل
MSA
مشرف عام
مشرف عام


عدد المساهمات : 542
تاريخ التسجيل : 16/06/2010

مُساهمةموضوع: رد: مراجع ودوائر وأعطال و شرح صيانة -CRT-LCD -plasma   الجمعة أبريل 22, 2011 3:03 am

PCB DG




Video Processor (VPC3210A)



Performed on a single chip processor VPC3210 contains high quality
video processor, which is designed for television sets with the format
4:3 and 16:9, Frequency 50/60 Hz and 100/120.
VPC3210 video processor has the following characteristics:




  • All video processing is done entirely in digital form.
  • Adaptive sharing scheme Y / C (luma / chroma), based on grabenchatogo
    Filter 2H (delay in 2H - 2 sweep period).
  • Multistandard color decoder PAL / NTSC / SECAM.
  • Integrated analog-digital converter.
  • Synchronization processing.
  • Horizontal scale.
  • Panomirovaniya function.
  • Clock generator synchronized with the frequency lines.


Analog preprocessor


This unit provides an analog interface for video input and,
basically, converts an analog-digital.
DCO (crystal oscillator clock with digital control).


Digital control quartz oscillator by digital signal processor.
Frequency clock can be adjusted in the range of ± 150 ppm.
Adaptive comb filter
Adaptive comb filter is used for high-end division
"Brightness / color" signals of PAL or NTSC. Comb filter
improves resolution in brightness (bandwidth) and reduces the noise level,
such spurious patterns caused by crosstalk, "color-brightness and
"Brightness-color." This adaptive algorithm can eliminate most
of the above errors without introducing new patterns or parasitic noise.
Color Decoder


This circuit performs the standard luma / chroma separation and multi-standard
demodulating the color signal. In the scheme of demodulating the color signal is used
asynchronous clock generator that allows to unify the architecture
standards for all systems of color television.
Scheme of horizontal scaling


Signal YIUV (brightness / chroma) from the decoder is processed by color
pattern of horizontal scaling. The main image is compressed and subjected to
interpolation on a percentage that is specified in the original data.

Synchronous Processing


Signal is formed of horizontal and vertical sync, which is then
served on weekends legs 14 and 12. Formed signals frequency 13.5 MHz and
27.0 MHz.
IIC bus
Relationship between unit VPC (video processor) and external control by
through the bus IIC. Leg 55 - Data SDA (data channel) Leg 56 - Clock SCL (channel
clock)


MULTI-WINDOW FUNCTIONS


With the help of integrated circuits IC1309 and IC1310 can perform the following functions.


  • Two windows
  • Gated all / part of the gated
  • Embedded image in the main image
  • Additional image outside the main image

Signal Y and UV signals are received from video processor VPC (IC1311) on the legs 120-127
and 112-119, sootvetstvenno.Zatem they are compressed and interpolated across.
Interpolation of these signals in the vertical by using the built-in
memory on the line. After that, with an external integrated circuit memory
on the field, these signals is compressed vertically. And in the end, the above
signal and the main image are mixed and disguised and served on
output.


V-PROCESSOR (Vertical Scan)


General Information


This V-CPU, which is part of UP-converter (with
increasing frequency), was specifically designed to aid in
display with interlaced scanning at a frequency 100/120 Hz to improve the quality
image.
V-processor has features that allow you to work with various
standards (formats) of the signal, for example: 4:1:1 or 4:2:2. This V-Processor
designed for operation in synchronous with the frequency of lines (Line-locked mode).

This ensures consistency in time for the synchronization signals
H / V (horizontal / vertical) is the same as that of the processed signal.

This video, which is also rigidly connected with the frequency of lines (Line-locked),
accompanied by synchronization signals H / V, which are converted to scan
with doubled frequency. This format scanner with double the frequency is the main
characteristic feature of the V-CPU.
In this processor scan signal is converted into a map with twice
frequency sweep. In addition, V-CPU is used to at
using digital signal processing to achieve the zoom (Zoom) pictures
in the vertical direction.
In previous models, the chassis with a frequency of 100 Hz for noise reduction.
In this model, the V-Protsesoore provides signal processing to suppress
interference. For this purpose, a special noise filter. This filter
adapts to the local motion picture. For this purpose, types of motion
divided into 4 categories. Decision made on the basis of three threshold
values ​​that are specified using the software for both luminance
and for color, independently of each other. And finally, the output V-Processor
suppresses the flickering images of large areas associated with the process of alternation
lines, and, moreover, increases the resolution of the active image. To
perform the processing of this type, V-processor is necessary to use a certain
Memory RAM (memory device with random access). Therefore,
RAM memory must have a full interface with the V-CPU. In addition, V-Processor
may have an additional function of freezing the image. This functional
feature is also known as "freeze-frame mode or
still image.
Aggregate data on the functional characteristics



  1. Interlace frequency of 100/120 Hz
  2. Suppression of flicker lines
  3. Interline flicker suppression
  4. The suppression of creep lines
  5. Scaling (stretching) along the vertical
  6. Interference rejection, adaptive with respect to the mean motion
  7. Freeze Frame
  8. Interface based on bus IIC.



FUNCTIONAL DESCRIPTION


Luminance signal, which comes from the output of the integrated circuit IC1309, comes
the input of the V-CPU through the legs 1, 2, 4, 5, 205-208.
While the color signal coming from the integrated circuit IC1309, comes
the input of the V-CPU on the legs 187, 188 and 190-195.
The main functions of V-CPU are as follows.

  • UP - Transformation (with increasing frequency).
  • Vertical panning.
  • Scaling.
  • Interference suppression.
  • Linear interpolation lines.

UP - The transformation is carried out through the following means:

  • Formation of additional fields for mode rotation frequency 100/120
    Hz.
  • Formation of new fields / frames for the implementation of scaling vertically.

Adaptive interference suppression scheme operated bus IIC. For luminance
and color, this scheme implemented with a filter with impulse response
infinite length (IIR filter) with a delay of a frame. To
avoid spurious patterns, used the scheme of interference suppression and
UP-conversion, controlled motion detection scheme based on frame
which works with the signal intensity. Operations in the schemes of interference suppression, detection
motion and the UP-conversion are performed using the memory circuits in the field. On
shown here, the figure shows the structure of V - CPU and main elements
memory. From this block diagram shows that the brightness and color signals are
on some routes, processing, and for each route requires two memory
on the field. Cascades of noise and motion detection process information
speed of incoming signals YUV. A cascade of UP-convert to process
and delivery of information at double speed. For motion detection is required
external memory blocks. These external memory blocks are needed for filtering
data traffic and for traffic flow information on a cascade of UP-conversion.
For communication with the scheme UP-conversion using the second output of the external blocks
memory.
Management by V-Processor via bus IIC. Internal diagram
Control (CTRL) V-processor is used to control external units
memory and other stages within a given integrated circuit.
Circuit Description


V-processor can be partitioned into separate blocks. Those listed below are the blocks
and will be described in this section.

  • Detection of motion (block MD)
  • Interference rejection (block NR)
  • Vertical filter (block VF)
  • Management
  • Output stage
  • Motion detection (MD)

The scheme of motion detection signal intensity, which comes
the input of the V-CPU through the legs 1, 2, 4, 5, and 205-208 with a frequency of 15.625 lines
MHz.
Cascade motion detection has two outputs, signals which are fed
at:

  • Suppression scheme (NR)
  • Vertical filter (VF)

For the detection (determination of the form) of the motion used one line from
current frame and one line from the previous frame. Information previous frame
kept in an external storage device, integrated circuit IC1303.
Required information frame is output through the legs 9, 11-12 V-Processor
and is included in the memory block frame (IC1303) via the leg 6-8. This information is then
protrudes from the integrated circuit memory frame through the legs of 9-11 and returns
back to V-processor and is inserted through the leg back to the 8.6 schema detection
movement. After that, the motion detector uses this information to control
as interference suppression scheme (NR), and the pattern of vertical filter (VF).
Interference rejection (NR)
Cascade suppression is used to reduce distortions in the main image
by averaging the two signals from successive scans, or frames. Such
interference suppression schemes are available in both routes of processing - as the luminance signal,
and chrominance. In order to implement noise suppression require external
memory blocks per frame and a string.
The advantage of the method of interference suppression based on frame compared to the method of suppression
interference on the basis of the field lies in the fact that in the first, thanks to the averaging of the line
X frame A0 and A1 lines x frame in which, as a result, averaged element
images in the same vertical position, remains a complete solution
vertically. While in the method of noise reduction based on the field is
smoothing along the vertical, resulting in a deterioration of resolution.

This is because the line X-1 from 0 and the string X are in different positions
vertically. If the motion detector determines a strong movement in video
the coefficient of interference suppression is set to a lower value on
Compared with those cases. when the motion is not detected at all (eg,
still image). This is because when applying a strong impact
suppression of fast motion video on an effect known
called "comet tail" or "toffee" (smear)
for objects moving across the screen.
Processing of luminance
Luminance signal passes through a cascade of suppression, where the signal is
the scheme of averaging. This served as the delayed signal intensity, which
enters through the input DYIN V-CPU (legs 13-14 and 16-21) and comes with an integral
memory circuits IC1303. In this circuit, this delayed luminance signal is subtracted
of the above are not the delayed signal, which provides lowering
interference. Then, the luminance signal with reduced noise comes from the cascade of suppression
interference, and is output through the V-CPU legs 138-141 and 143-146 (YNROUT),
where it comes from on the integrated circuit blocks of external memory IC1302. From these
memory block luminance signal is introduced back to the V-CPU through 86-98 feet
(VFIN) and falls on the vertical filter (VF).
Processing of chrominance
Interference suppression for color signal in exactly the same as for
considered above, the luminance signal. However. processing route, of course, on the other.
Color signal arrives at the V-CPU through the findings UVIN (leg 187, 188
and 190-195). Hence the color signal is fed to a cascade of noise and goes
the scheme of averaging. Here served as a detainee color signal, which
enters through the input DUVIN (170-173 feet) and comes with an integrated circuit memory
IC1301 and subjected to homogenization with a non-delayed signal chromaticity. This provides
significant reduction in the level of interference in a signal color. Then the color signal
low level of interference comes from the cascade of noise and served on
Output V-CPU through outputs UVNROUT (124-127 feet, 128, 129, 132, 133),
where it comes from on the integrated circuit blocks of external memory IC1301 and IC1302.

Vertical filter (VF)
In addition, the motion detector applied to the output signal information on the vertical
filter, which is used to perform linear interpolation line and the suppression
flickering lines. This vertical filter is a key element of the V-CPU,
because it is used for linear interpolation of the line, the result is
depends on the information received from the motion detector. To perform the interpolation
requires the following signals:
Luminance

  • VFIN, legs 81-84, 86-93, coming from the integrated circuit IC1302
  • DLYIN, with 148-156 feet coming from the integrated circuit IC1302
  • YVFIN, legs 64-76, coming from the integrated circuit IC303.

Output terminals DLYOUT (leg 22-25, 28-31) share information with the V-CPU
on an integrated circuit memory IC1303. Chrominance signal

  • UVVFIN, legs 81-84, coming from the integrated circuit IC1721.
  • DUVIN, stem 174-175/177-178, coming from the integrated circuit IC1302
  • DUVIN, 115-118 feet, coming from the integrated circuit IC1724.

Reading of information from the above-mentioned integrated circuit memory is
double speed. That is, the signals are read at the entrance with a frequency of 16
kc, read the output with a frequency of 32 kHz. As a result, this translates into
that each field (half frame) is reproduced on the screen twice. Frequency
personnel increased from 50 to 100 Hz. As a result, large areas of flicker
image inherent in a television receiver with a frequency of 50 Hz decreases.
As a byproduct of this block of memory it should be noted, also,
the possibility of obtaining a still image. This result is achieved
using the control channel, which consists of the legs 105, 161, 196, included
series with memory blocks on a field that is used to preostanovit
overwrite the old image data and information movement. In the freezing
images can still use the zoom mode and vertical
panaromirovaniya mode. This allows you to enlarge a specific area
screen.
Blocks of memory on the field and the line
From the above block diagram shows that there are three integrated circuit memory.
This integrated circuit memory of Siemens brand SDA9251 and SDA9253, which
are dynamic blocks of memory with serial access designed
for use in television (TV-SAM).
Integrated circuits such as SDA is a dynamic memory blocks serial
access with built-in ports, which are intended for processing
video with high speed data transmission. They are organized like
read: 212 series 64 speakers and 16 sets of 4 bits. This allows us to keep
in memory of 4-bit planes of television (TV) fields (NTSC, PAL, SECAM) with
standard or studio (wired) quality. Schema standard TV-SAM apply
in blocks of memory on the field and on line. IC IC1303, which is served
signal DL-YOUT, uses this signal to generate a signal DYIN.
This latter signal is used to detect motion. Integral
circuit memory IC1303, which operates at clock pulses, accounting for half
from the system clock as the input and output, is used
in order to obtain the necessary information movement.


BLOCK DFU (Block digital features)



To improve the quality of the image block is used FJB007, which performs
this problem by improving the quality of signals color, black and white. Except
order to enhance the contrast, here we use the expansion level
black.

  • Input for digital AI

    Signal Y (brightness) / leg 37, 39-42, 44, 45, 63
    Signal UV (chroma) / 54-59 feet, 52
  • Log in to automatically format

    Signal Y (brightness) / 75-82 feet
    Signal UV (chroma) / 65-72 feet

Adaptive scheme YNR (suppression luminance signal)
This scheme is quantitatively detects (determines) the noise level during the blanking
Vertical refresh the image signal (YIN). Then, the period in which
can be made removing interference is automatically changed in accordance
with diagnosed by detecting the level of interference. Scheme AI (Artificial Intelligence
- Artificial Intelligence) This scheme allows you to make a more natural improvement
in image quality in the scheme scales smaller than the standard.

Sharpness of the vertical
In this scheme, there are two blocks of memory on the line for the luminance signal and 1 block
memory (latency 1H) for chroma. Before the advent of the image
required to produce two difference calculations involving the three pieces of information.
In the received signal, in addition to the original signal, this scheme establishes
limitations in the perpendicular direction.
Sharpness of the horizontal
The same as in the scheme AN5342
High-frequency correction (emphasis circuits) In this scheme uses
information Y / C (luma / chroma), obtained after treatment with two screens.
This scheme checks the line and the image detail in the signal. Since
of review (audit) of the line, then running the scheme VM (velocity modulation).
It creates an image that is hard to see at the boundary of the 2 screens.
Therefore, this scheme generates momentum which suspends the scan line
for some additional positions in the horizontal direction, corresponding
the time when such decision was taken. This scheme, in accordance with
control pulse, checks the boundary region.
CTI (chroma noise suppression)
Checks the line for the signal UV (chroma)
CRI (Improved resolution in color)
This circuit receives the input signal to UV (chroma) and regulates the action at the level of
Unit test line in the part that refers to the fluctuations with large
amplitude.
VM (velocity modulation)
That part of the scheme, in which the signal is formed VM, produces the output signal
obtained by calculating the 1-st derivative of the luminance signal, as
signal VM.
Automatic formatting (Samoformatirovanie)
This circuit detects the position of a framework character image at the top
part of the image, position the bottom of the image and the position of credits
in these images. The scheme transmits this information via the IIC bus to the microprocessor
MPU.
الرجوع الى أعلى الصفحة اذهب الى الأسفل
MSA
مشرف عام
مشرف عام


عدد المساهمات : 542
تاريخ التسجيل : 16/06/2010

مُساهمةموضوع: رد: مراجع ودوائر وأعطال و شرح صيانة -CRT-LCD -plasma   الجمعة أبريل 22, 2011 3:04 am

PCB DG




Video Processor (VPC3210A)



Performed on a single chip processor VPC3210 contains high quality
video processor, which is designed for television sets with the format
4:3 and 16:9, Frequency 50/60 Hz and 100/120.
VPC3210 video processor has the following characteristics:




  • All video processing is done entirely in digital form.
  • Adaptive sharing scheme Y / C (luma / chroma), based on grabenchatogo
    Filter 2H (delay in 2H - 2 sweep period).
  • Multistandard color decoder PAL / NTSC / SECAM.
  • Integrated analog-digital converter.
  • Synchronization processing.
  • Horizontal scale.
  • Panomirovaniya function.
  • Clock generator synchronized with the frequency lines.


Analog preprocessor


This unit provides an analog interface for video input and,
basically, converts an analog-digital.
DCO (crystal oscillator clock with digital control).


Digital control quartz oscillator by digital signal processor.
Frequency clock can be adjusted in the range of ± 150 ppm.
Adaptive comb filter
Adaptive comb filter is used for high-end division
"Brightness / color" signals of PAL or NTSC. Comb filter
improves resolution in brightness (bandwidth) and reduces the noise level,
such spurious patterns caused by crosstalk, "color-brightness and
"Brightness-color." This adaptive algorithm can eliminate most
of the above errors without introducing new patterns or parasitic noise.
Color Decoder


This circuit performs the standard luma / chroma separation and multi-standard
demodulating the color signal. In the scheme of demodulating the color signal is used
asynchronous clock generator that allows to unify the architecture
standards for all systems of color television.
Scheme of horizontal scaling


Signal YIUV (brightness / chroma) from the decoder is processed by color
pattern of horizontal scaling. The main image is compressed and subjected to
interpolation on a percentage that is specified in the original data.

Synchronous Processing


Signal is formed of horizontal and vertical sync, which is then
served on weekends legs 14 and 12. Formed signals frequency 13.5 MHz and
27.0 MHz.
IIC bus
Relationship between unit VPC (video processor) and external control by
through the bus IIC. Leg 55 - Data SDA (data channel) Leg 56 - Clock SCL (channel
clock)


MULTI-WINDOW FUNCTIONS


With the help of integrated circuits IC1309 and IC1310 can perform the following functions.


  • Two windows
  • Gated all / part of the gated
  • Embedded image in the main image
  • Additional image outside the main image

Signal Y and UV signals are received from video processor VPC (IC1311) on the legs 120-127
and 112-119, sootvetstvenno.Zatem they are compressed and interpolated across.
Interpolation of these signals in the vertical by using the built-in
memory on the line. After that, with an external integrated circuit memory
on the field, these signals is compressed vertically. And in the end, the above
signal and the main image are mixed and disguised and served on
output.


V-PROCESSOR (Vertical Scan)


General Information


This V-CPU, which is part of UP-converter (with
increasing frequency), was specifically designed to aid in
display with interlaced scanning at a frequency 100/120 Hz to improve the quality
image.
V-processor has features that allow you to work with various
standards (formats) of the signal, for example: 4:1:1 or 4:2:2. This V-Processor
designed for operation in synchronous with the frequency of lines (Line-locked mode).

This ensures consistency in time for the synchronization signals
H / V (horizontal / vertical) is the same as that of the processed signal.

This video, which is also rigidly connected with the frequency of lines (Line-locked),
accompanied by synchronization signals H / V, which are converted to scan
with doubled frequency. This format scanner with double the frequency is the main
characteristic feature of the V-CPU.
In this processor scan signal is converted into a map with twice
frequency sweep. In addition, V-CPU is used to at
using digital signal processing to achieve the zoom (Zoom) pictures
in the vertical direction.
In previous models, the chassis with a frequency of 100 Hz for noise reduction.
In this model, the V-Protsesoore provides signal processing to suppress
interference. For this purpose, a special noise filter. This filter
adapts to the local motion picture. For this purpose, types of motion
divided into 4 categories. Decision made on the basis of three threshold
values ​​that are specified using the software for both luminance
and for color, independently of each other. And finally, the output V-Processor
suppresses the flickering images of large areas associated with the process of alternation
lines, and, moreover, increases the resolution of the active image. To
perform the processing of this type, V-processor is necessary to use a certain
Memory RAM (memory device with random access). Therefore,
RAM memory must have a full interface with the V-CPU. In addition, V-Processor
may have an additional function of freezing the image. This functional
feature is also known as "freeze-frame mode or
still image.
Aggregate data on the functional characteristics



  1. Interlace frequency of 100/120 Hz
  2. Suppression of flicker lines
  3. Interline flicker suppression
  4. The suppression of creep lines
  5. Scaling (stretching) along the vertical
  6. Interference rejection, adaptive with respect to the mean motion
  7. Freeze Frame
  8. Interface based on bus IIC.



FUNCTIONAL DESCRIPTION


Luminance signal, which comes from the output of the integrated circuit IC1309, comes
the input of the V-CPU through the legs 1, 2, 4, 5, 205-208.
While the color signal coming from the integrated circuit IC1309, comes
the input of the V-CPU on the legs 187, 188 and 190-195.
The main functions of V-CPU are as follows.

  • UP - Transformation (with increasing frequency).
  • Vertical panning.
  • Scaling.
  • Interference suppression.
  • Linear interpolation lines.

UP - The transformation is carried out through the following means:

  • Formation of additional fields for mode rotation frequency 100/120
    Hz.
  • Formation of new fields / frames for the implementation of scaling vertically.

Adaptive interference suppression scheme operated bus IIC. For luminance
and color, this scheme implemented with a filter with impulse response
infinite length (IIR filter) with a delay of a frame. To
avoid spurious patterns, used the scheme of interference suppression and
UP-conversion, controlled motion detection scheme based on frame
which works with the signal intensity. Operations in the schemes of interference suppression, detection
motion and the UP-conversion are performed using the memory circuits in the field. On
shown here, the figure shows the structure of V - CPU and main elements
memory. From this block diagram shows that the brightness and color signals are
on some routes, processing, and for each route requires two memory
on the field. Cascades of noise and motion detection process information
speed of incoming signals YUV. A cascade of UP-convert to process
and delivery of information at double speed. For motion detection is required
external memory blocks. These external memory blocks are needed for filtering
data traffic and for traffic flow information on a cascade of UP-conversion.
For communication with the scheme UP-conversion using the second output of the external blocks
memory.
Management by V-Processor via bus IIC. Internal diagram
Control (CTRL) V-processor is used to control external units
memory and other stages within a given integrated circuit.
Circuit Description


V-processor can be partitioned into separate blocks. Those listed below are the blocks
and will be described in this section.

  • Detection of motion (block MD)
  • Interference rejection (block NR)
  • Vertical filter (block VF)
  • Management
  • Output stage
  • Motion detection (MD)

The scheme of motion detection signal intensity, which comes
the input of the V-CPU through the legs 1, 2, 4, 5, and 205-208 with a frequency of 15.625 lines
MHz.
Cascade motion detection has two outputs, signals which are fed
at:

  • Suppression scheme (NR)
  • Vertical filter (VF)

For the detection (determination of the form) of the motion used one line from
current frame and one line from the previous frame. Information previous frame
kept in an external storage device, integrated circuit IC1303.
Required information frame is output through the legs 9, 11-12 V-Processor
and is included in the memory block frame (IC1303) via the leg 6-8. This information is then
protrudes from the integrated circuit memory frame through the legs of 9-11 and returns
back to V-processor and is inserted through the leg back to the 8.6 schema detection
movement. After that, the motion detector uses this information to control
as interference suppression scheme (NR), and the pattern of vertical filter (VF).
Interference rejection (NR)
Cascade suppression is used to reduce distortions in the main image
by averaging the two signals from successive scans, or frames. Such
interference suppression schemes are available in both routes of processing - as the luminance signal,
and chrominance. In order to implement noise suppression require external
memory blocks per frame and a string.
The advantage of the method of interference suppression based on frame compared to the method of suppression
interference on the basis of the field lies in the fact that in the first, thanks to the averaging of the line
X frame A0 and A1 lines x frame in which, as a result, averaged element
images in the same vertical position, remains a complete solution
vertically. While in the method of noise reduction based on the field is
smoothing along the vertical, resulting in a deterioration of resolution.

This is because the line X-1 from 0 and the string X are in different positions
vertically. If the motion detector determines a strong movement in video
the coefficient of interference suppression is set to a lower value on
Compared with those cases. when the motion is not detected at all (eg,
still image). This is because when applying a strong impact
suppression of fast motion video on an effect known
called "comet tail" or "toffee" (smear)
for objects moving across the screen.
Processing of luminance
Luminance signal passes through a cascade of suppression, where the signal is
the scheme of averaging. This served as the delayed signal intensity, which
enters through the input DYIN V-CPU (legs 13-14 and 16-21) and comes with an integral
memory circuits IC1303. In this circuit, this delayed luminance signal is subtracted
of the above are not the delayed signal, which provides lowering
interference. Then, the luminance signal with reduced noise comes from the cascade of suppression
interference, and is output through the V-CPU legs 138-141 and 143-146 (YNROUT),
where it comes from on the integrated circuit blocks of external memory IC1302. From these
memory block luminance signal is introduced back to the V-CPU through 86-98 feet
(VFIN) and falls on the vertical filter (VF).
Processing of chrominance
Interference suppression for color signal in exactly the same as for
considered above, the luminance signal. However. processing route, of course, on the other.
Color signal arrives at the V-CPU through the findings UVIN (leg 187, 188
and 190-195). Hence the color signal is fed to a cascade of noise and goes
the scheme of averaging. Here served as a detainee color signal, which
enters through the input DUVIN (170-173 feet) and comes with an integrated circuit memory
IC1301 and subjected to homogenization with a non-delayed signal chromaticity. This provides
significant reduction in the level of interference in a signal color. Then the color signal
low level of interference comes from the cascade of noise and served on
Output V-CPU through outputs UVNROUT (124-127 feet, 128, 129, 132, 133),
where it comes from on the integrated circuit blocks of external memory IC1301 and IC1302.

Vertical filter (VF)
In addition, the motion detector applied to the output signal information on the vertical
filter, which is used to perform linear interpolation line and the suppression
flickering lines. This vertical filter is a key element of the V-CPU,
because it is used for linear interpolation of the line, the result is
depends on the information received from the motion detector. To perform the interpolation
requires the following signals:
Luminance

  • VFIN, legs 81-84, 86-93, coming from the integrated circuit IC1302
  • DLYIN, with 148-156 feet coming from the integrated circuit IC1302
  • YVFIN, legs 64-76, coming from the integrated circuit IC303.

Output terminals DLYOUT (leg 22-25, 28-31) share information with the V-CPU
on an integrated circuit memory IC1303. Chrominance signal

  • UVVFIN, legs 81-84, coming from the integrated circuit IC1721.
  • DUVIN, stem 174-175/177-178, coming from the integrated circuit IC1302
  • DUVIN, 115-118 feet, coming from the integrated circuit IC1724.

Reading of information from the above-mentioned integrated circuit memory is
double speed. That is, the signals are read at the entrance with a frequency of 16
kc, read the output with a frequency of 32 kHz. As a result, this translates into
that each field (half frame) is reproduced on the screen twice. Frequency
personnel increased from 50 to 100 Hz. As a result, large areas of flicker
image inherent in a television receiver with a frequency of 50 Hz decreases.
As a byproduct of this block of memory it should be noted, also,
the possibility of obtaining a still image. This result is achieved
using the control channel, which consists of the legs 105, 161, 196, included
series with memory blocks on a field that is used to preostanovit
overwrite the old image data and information movement. In the freezing
images can still use the zoom mode and vertical
panaromirovaniya mode. This allows you to enlarge a specific area
screen.
Blocks of memory on the field and the line
From the above block diagram shows that there are three integrated circuit memory.
This integrated circuit memory of Siemens brand SDA9251 and SDA9253, which
are dynamic blocks of memory with serial access designed
for use in television (TV-SAM).
Integrated circuits such as SDA is a dynamic memory blocks serial
access with built-in ports, which are intended for processing
video with high speed data transmission. They are organized like
read: 212 series 64 speakers and 16 sets of 4 bits. This allows us to keep
in memory of 4-bit planes of television (TV) fields (NTSC, PAL, SECAM) with
standard or studio (wired) quality. Schema standard TV-SAM apply
in blocks of memory on the field and on line. IC IC1303, which is served
signal DL-YOUT, uses this signal to generate a signal DYIN.
This latter signal is used to detect motion. Integral
circuit memory IC1303, which operates at clock pulses, accounting for half
from the system clock as the input and output, is used
in order to obtain the necessary information movement.


BLOCK DFU (Block digital features)



To improve the quality of the image block is used FJB007, which performs
this problem by improving the quality of signals color, black and white. Except
order to enhance the contrast, here we use the expansion level
black.

  • Input for digital AI

    Signal Y (brightness) / leg 37, 39-42, 44, 45, 63
    Signal UV (chroma) / 54-59 feet, 52
  • Log in to automatically format

    Signal Y (brightness) / 75-82 feet
    Signal UV (chroma) / 65-72 feet

Adaptive scheme YNR (suppression luminance signal)
This scheme is quantitatively detects (determines) the noise level during the blanking
Vertical refresh the image signal (YIN). Then, the period in which
can be made removing interference is automatically changed in accordance
with diagnosed by detecting the level of interference. Scheme AI (Artificial Intelligence
- Artificial Intelligence) This scheme allows you to make a more natural improvement
in image quality in the scheme scales smaller than the standard.

Sharpness of the vertical
In this scheme, there are two blocks of memory on the line for the luminance signal and 1 block
memory (latency 1H) for chroma. Before the advent of the image
required to produce two difference calculations involving the three pieces of information.
In the received signal, in addition to the original signal, this scheme establishes
limitations in the perpendicular direction.
Sharpness of the horizontal
The same as in the scheme AN5342
High-frequency correction (emphasis circuits) In this scheme uses
information Y / C (luma / chroma), obtained after treatment with two screens.
This scheme checks the line and the image detail in the signal. Since
of review (audit) of the line, then running the scheme VM (velocity modulation).
It creates an image that is hard to see at the boundary of the 2 screens.
Therefore, this scheme generates momentum which suspends the scan line
for some additional positions in the horizontal direction, corresponding
the time when such decision was taken. This scheme, in accordance with
control pulse, checks the boundary region.
CTI (chroma noise suppression)
Checks the line for the signal UV (chroma)
CRI (Improved resolution in color)
This circuit receives the input signal to UV (chroma) and regulates the action at the level of
Unit test line in the part that refers to the fluctuations with large
amplitude.
VM (velocity modulation)
That part of the scheme, in which the signal is formed VM, produces the output signal
obtained by calculating the 1-st derivative of the luminance signal, as
signal VM.
Automatic formatting (Samoformatirovanie)
This circuit detects the position of a framework character image at the top
part of the image, position the bottom of the image and the position of credits
in these images. The scheme transmits this information via the IIC bus to the microprocessor
MPU.
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عدد المساهمات : 542
تاريخ التسجيل : 16/06/2010

مُساهمةموضوع: رد: مراجع ودوائر وأعطال و شرح صيانة -CRT-LCD -plasma   الجمعة أبريل 22, 2011 3:06 am

SUPPLY SCHEME



SCHEME SWITCHING AC input voltage



DESCRIPTION
In this chassis used a scheme of automatic control input
AC voltage in the range 110 - 240V.
For the input AC 145v or below the value of this scheme works as
voltage doubler, while the voltage is higher than 145v as a bridge rectifier.
Operations performed by the scheme D801/TRIAC (symmetrical diode thyristor)
Diode bridge D801, together with a transistor Q3, capacitor S817 and S818,
operates as a voltage doubler (Q3: ON (on)) or as a bridging
rectifier (D801: OFF (switched off)).

[ندعوك للتسجيل في المنتدى أو التعريف بنفسك لمعاينة هذه الصورة]
Figure 1
SENSING AC input voltage




  1. When AC voltage is first fed to
    input, it passes poluperiodnoe rectification rectifier integral
    circuit IC813.

  2. Then, this DC voltage applied to the zener
    (Tunnel) diode D1.

  3. In the case where the AC voltage is equal to or
    exceeds the 145v, the DC voltage on the cathode of the diode D1 exceeds
    zener voltage and includes (ON) this diode, which creates a drop
    voltage across the resistor R1.

  4. Formed on this resistance voltage includes
    transistor Q1.

  5. When the transistor Q1 is opened, the diode D2 turns off
    and thus turns off transistor Q2.

  6. When the transistor Q2 is turned off (OFF), then off, as well
    and the transistor Q3 and, as a result, it forms a regular Bridge rectifier.

  7. In the case where the AC voltage is less than
    145v, diode D1 is closed (OFF), the transistor Q1 is turned off (OFF) and opens
    (ON) diode D2.

  8. When the diode D2 is opened (ON), then open (ON) transistor
    Q2 and the gate current symmetric triode thyristor flows through the resistor
    R2, and includes the device.

  9. When balanced triode thyristor Q3 included (ON),
    it forms a voltage doubler rectifier.

AMPLIFIERS



BRIDGE AMPLIFIER (Transistor Q3 is turned off (OFF))

  1. In the case when the input AC voltage exceeds 145v,
    simmerichny triode thyristor Q3 is turned off (OFF).
  2. Positive and negative half-cycles of the input AC charge
    Both S817 and S818 of the capacitor. Thus forming a two-poluperiodny
    rectifier. In the case when the input AC voltage is
    200V:
    DC voltage = 200 • the square root of 2 = 280V


RECTIFIER - voltage doubler (Transistor Q3 is included (ON))

  1. When the input AC voltage less than 145v, balanced
    triode thyristor Q3 included (ON).
  2. Positive half-cycle AC input current charges capacitor
    S817, and the negative half-cycle charges the capacitor S818. Thus
    formed by the rectifier-doubler.
    In the case when the input AC voltage is 100V:
    DC voltage on the capacitors S817 = 100 • square root
    from 2 = 140V;
    DC voltage on the capacitors S818 = 100 • square root
    from 2 = 140V
  3. Thus the output voltage is 280V.


CHIEF Switching Regulator



[ندعوك للتسجيل في المنتدى أو التعريف بنفسك لمعاينة هذه الصورة]
Figure 2
OPERATION SCHEME LAUNCH

  1. When the applied ac voltage, the current flows through
    diode D802 and resistors R803 and R804. During the capacitor charging S839 on the screen
    displayed launching stress on the leg 5 of the integrated circuit IC813.
    In that case, when launching the voltage reaches 23 in the Field
    Transistor FET starts to give out trigger pulse (point as well. Figure 3).
  2. At the beginning of the transistor FET, with a capacitor S839 prodolzheyutsya
    fluctuations in supply voltage (point b. Figure 3).
  3. With the launch of the FET FET with coil displacement through T802
    Diode D822 serves for five legs of the integrated circuit IC813 stress enough
    to maintain oscillations.
  4. If the voltage of the diode D822 is not received, the voltage on the capacitor
    S839 decreases, as shown at the point with. (Figure 3). When this voltage
    falls to a voltage shutdown (15.2 in), the oscillations cease.


[ندعوك للتسجيل في المنتدى أو التعريف بنفسك لمعاينة هذه الصورة]
Figure 3

VIBRATION PATTERN



[ندعوك للتسجيل في المنتدى أو التعريف بنفسك لمعاينة هذه الصورة]
Figure 4


  1. Scheme fluctuations constructed from a capacitor C2 connected to the withdrawal of T-ON
    oscillator OSC, and capacitors C3 and C4, are connected with the withdrawal of T-OFF. This
    circuit generates pulses, which include field-effect transistor FET.
  2. When the voltage on the leg 5 of the integrated circuit reaches the trigger
    voltage to the gate of the FET FET a pulse "H"
    (High). At the same time, the output T-ON voltage is applied, which gradually
    charges capacitor C2. Once this voltage reaches a value of 0.75 in
    output current pulse oscillation changes its value at L (low) and Field
    FET transistor is switched off. Then, the voltage output T-ON is quickly discharged
    to 0 in the discharge through the circuit.
  3. When the field-effect transistor FET is turned on, capacitor C3, connected to the output
    T-OFF, charging up to a certain voltage (4,5).
  4. As soon as the voltage at T-ON reaches a value of 0.75 in, then the charge
    V 4.5 in the capacitor C3 is discharged during a given period
    through a resistor R4. When this voltage reaches 2.7 V, the output
    signal oscillation circuit again inverted and the gate of the FET
    FET is given stress level H (high), which includes (ON) MOSFET
    FET. At this time, capacitor C3 is charged up again to 4.5. Normal value
    On-time field-effect transistor FET ON voltage is given by
    on output at TDL, which will be considered in the next section.
  5. The power supply to the output T-ON capacitor C2 is regulated with terminal
    6 feet of feedback (FB). When the capacitor C2 is discharged, while the inclusion
    (ON) field-effect transistor FET is used to stabilize voltage + V2.

SCHEME soft launch

  1. When power voltage of 3 V, supplied from the legs 7, provides
    charging current for capacitor S837 and increases tension leg 4, discharging
    with decreasing voltage.
  2. At this time, after power-current MOSFET increases
    medlenno.Poetomu throw current when the power can be suppressed.


Table 1
Protection scheme Leg detection Conditions of work
OVP Leg 5 more 33B
TSD Internal chip More than 150 ° C
OVP.nozhka 7 Voltage pins 7 more than 10c

Scheme locking (locking scheme)

  1. Locking scheme is a scheme of protection against overvoltage,
    which consists of the protection circuit against excess voltage (ODP)
    overheat protection circuit (TSD) and the legs 7. Working conditions for each of these
    schemes are discussed below. During operation of these schemes work of launching the scheme
    pulse is terminated.
  2. At the beginning of the circuit locking started working regulatory scheme
    food (REG), and operations for issuing output signals are terminated. Therefore,
    stress on the leg 5 rises and falls between the values ​​of 23B and in 15.2.
  3. To stop blocking schemes need to turn off the main power supply.


PATTERNS OF CONSTANT VOLTAGE




  1. Managing stress + B2, carried out with a leg of the integrated circuit
    IC814, is intended to reduce changes due to negative
    fluctuations in the voltage + B, which is the output voltage
    DC, as well as voltage fluctuations of + B2, which is a fluctuation
    AC.
  2. When the voltage on pin 1 of integrated circuit IC814 is increased,
    also reduce stress on the leg 2, increasing the light emitted diode D827.
  3. By increasing the flow of light emitted by the diode D827, the voltage on
    leg 6 of the integrated circuit IC813 increases. Thereby increasing the current entering
    the withdrawal of T-ON, affecting the charging of the capacitor C2.
  4. When charging the capacitor C2 becomes shorter, while the inclusion
    (ON) field-effect transistor FET is reduced and the oscillation frequency increases
  5. With a decrease in on-time (ON) MOSFET FET oscillation frequency
    increases and voltage + V2 is reduced.
  6. The above operation is stabilized voltage + B2



Switching Regulator Standby


+12 V for the standby mode when power is applied, which straightens
poluperiodnym rectifier diodes D805 and D848, it starts to work the integral
circuit IC802. This wave is rectangular in shape with a frequency around 100 kHz is applied
on field-effect transistor FET and arranges to switch between the legs 2 and 3.
When switching FET FET energy flows into the secondary obmrtku
transformer T801. When performing the above operations generated voltage
+12. It detects the changing voltage of the voltage on the diode D812,
D809. Subsequently, the variable part comes to integrated circuit IC802. In
those circumstances where there is a change of the stress in 12c, it is carried out
follows.

Table 2
12c,
Exit
The light diode
D809
Scheme
IC802 "1".
Frequency
circuit IC802
12c,
Exit

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[ندعوك للتسجيل في المنتدى أو التعريف بنفسك لمعاينة هذه الصورة]


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[ندعوك للتسجيل في المنتدى أو التعريف بنفسك لمعاينة هذه الصورة]


This integrated circuit IC802 has a protective circuit, which acts against
over current and temperature rise. The work of the integrated circuit stops
when the temperature of the scheme exceeds 150 degrees Celsius.

Protection Scheme



Normal operation
12V is formed when you turn the main power supply and at the beginning of the
microprocessor MPU. Voltage H1 is output from the legs 52 MPU.
Standby mode is created at a time when transistor Q804 is enabled (ON), and the transistor
Q801 is turned off (OFF). Nutrition is given scheme Remocon and low-voltage power
is output from the legs 52 MPU. Terms of power
(ON): the transistor Q801 is enabled (ON), and the scheme RL801 is also included (ON).
Protection scheme
There are 8 types of protection schemes.
After triggering the protection circuit arise following conditions: collector transistor
Q802 is low (Low);
Transistor Q801 is turned off (OFF), so the power is off (OFF). Voltage
base of the transistor Q803 is lowered, the transistor Q803
enabled (ON). Therefore, the transistor Q802 conducts (ON). Hence it is necessary
adjust the power supply by control
protection scheme.

  1. Short-circuit protection circuit (capacitor S818)
    When triggered circuit short circuit S818, it triggered a diode D849
    (ON). Through the transistor Q806 begins to pass an electric current, which
    passes through the diode D810 and transistor Q802 collector sets the low
    level.
  2. Protection circuit against excess voltage (S818)
    When the capacitor S818 arrives too high voltage, the diode D806
    open (ON). Through the transistor Q806 begins to flow electrical current which
    passes through the diode D810 and transistor Q802 collector sets the low
    level.
  3. Protection scheme UNT (Optional high voltage)
    For the collector of the transistor Horizontal connected capacitors
    S514, S515, S516. They are used for voltage detection UNT. If you have any
    excessively high voltage activated (ON) diode D516 and transistor Q802.
  4. Short-circuit protection circuit voltage + B
    By lowering the signal (standby) STBY 5V, 14V, 140V, 32V and Sound,
    16V, 50V, 24V to 0V, the transistor Q502 collector is set at the level of
    H, and the transistor Q802 is included (ON).
  5. Over current scheme for the vertical stress 15c.
    Detection of the current vertical refresh in the 15th century made the transistor
    Q512. If there is too strong a current it flows through the diode D507
    and open (ON) transistor Q802.
  6. Over current scheme for 140V.
    Detection of the current channel at 140V by transistor Q810. When
    occurrence of too strong a current it flows through the diode D835 and opens
    (ON) transistor Q802.
  7. Scheme over voltage 140V.
    Detection voltage for channel 140V by using resistors
    R856, R855. If there is too Silone voltage diode D835 opens
    (ON) and open (ON) transistor Q802.
  8. Protection circuit against excess voltage heater
    Heater voltage is detected by a schema consisting of D871,
    C871, R871, R872. If there is too much high-voltage open
    (ON) diode D872 and transistor Q802.
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عدد المساهمات : 542
تاريخ التسجيل : 16/06/2010

مُساهمةموضوع: رد: مراجع ودوائر وأعطال و شرح صيانة -CRT-LCD -plasma   الجمعة أبريل 22, 2011 3:07 am

SOUND



SCHEME MSP


Similarly tkzhe as the chassis EURO, which is produced in the UK / MELUK, in this chassis
audio signal is formed as a dual-frequency-modulated stereo signal
which is processed by audio processor MSP3410. In addition,
part of this scheme include audio demodulation scheme, which in normal
mode is realized on the stage of intermediate frequency. Along with the processing of analog
audio signal processing circuit MSP3410 also signals NICAM, which come
with a cascade of intermediate frequency.
MSP scheme is a Multi-technology sound processor, which is used
for processing analog and digital television signals. On this single integrated
scheme is fully satisfied all the sound processing a television signal,
from the cascade of sound intermediate frequency.
MSP3410 scheme was designed to simultaneously perform digital demodulation
and decoding TV sound stereo signals encoded in the system
NICAM, and demodulation of frequency-modulated mono audio television signals.
On the other hand, using MSP3410 processor can also handle two
frequency modulated stereo signal.
However, when receiving an amplitude-modulated sound carrier, after demodulation,
which is still performed on stage intermediate frequency signal is
Mono inputs to the output circuit MSP for further processing.
Processor MSP3410 offers the following advantages:

  1. Two are available for selection of analog input (depends on model)
  2. Automatic gain control (AGC) for analog input
  3. Built-in converter A / D (analog-digital) for input sound stage
    intermediate frequency
  4. All the schemes of demodulation and filtering are implemented in one chip
  5. Easily switch between the two standards NICAM (NICAM BG / I) (MULTIPLEXER
    system almost immediately assignment)
  6. Requires only one crystal oscillator to set the clock
    (18.432 MHz)
  7. Detection of frequency-modulated carrier to carrier suppression function


[ندعوك للتسجيل في المنتدى أو التعريف بنفسك لمعاينة هذه الصورة]
Figure 1

SCHEME DSP and AI


Appointment
Filing sound effects implemented integrated circuit IC2402 DSP (Digital
sound processor) using the audio signals L and R, are selected integral
scheme IC3001. In order to provide surround sound (the sounds of the external
environment) for the signals L and R are used IC IC2401. Except
In addition, this processor generates sound center speaker, which
confirms (focuses) the type of sound (music, speech), and provides automatic
adjust bass and treble sounds.
The scheme of DSP
Sound signals are fed to the integrated circuit IC2402 on the legs 8 and 9,
pass through a scheme of killing and come directly to the mixing scheme. Hence, they
selected for the scheme of DSP, where these signals and sound effects are converted into
digital form. (In this chassis does not use the scheme LPF (BPF)
and NR (noise reduction)). In the scheme of DSP, this signal undergoes a transformation
A / D (analog-digital) with a clock frequency of 8MHz. And the sound effects (the stadium, home,
cinema) are created in digital form. After conversion, D / A (digital-analog)
These signals are synthesized with the original sound with the mixer and fed
the output to the legs 16 and 15.
Sound Scheme AI
Input level of audio signals L and R, arriving at the legs 30 and an integral
scheme IC2401, detected by the sensor level AGC. These signals are then
are used for different types of management. Synthesizing sounds L and R by
with mixer A. Here is formed by the sound of the center speaker,
which is input into a mono signal (monaural signal) on the leg
27.
Difference schemes in sends a signal difference between the signals of a stereo audio L and
R to the diagram of the phase shift. To create the effect of environment signals L and R are synthesized
with mixing-difference scheme S. For a mono-sound (monaural)
transistor Q2404 turns off the sound with the legs 27 pass through the bandpass filter
and served on the leg 26. Here there is a strengthening low tones and sounds of L and R
synthesized by mixing D to create the effect of the environment.
In the setup of low and high tones of the presence of sounds of L and R, which come
on an integrated circuit IC1213 MPU, when a sound AI scheme is enabled,
255 times every 4 ms by a microprocessor MPU. Is this sound
music or speech is determined based on the content of the reference OPTION FACTORY NORMAL
4 (factory-normal). then served with a control scheme DAC (controller
digital-analog) and automatic adjustment of low and high tones
IC IC2401.

Table 1
The number of times the appearance
vysokogourovnya voltage
Result
determination
Sound AI1 <30 times No sound
Sound AI2 <60 times Speech
Sound AI3 > 240 times Stereo
To adjust the sound via the IIC bus to the microprocessor MPU control signals are fed
VOL (volume) and the DAC. Sounds L, R and Center (central) go from the legs 19,
11 and 18, respectively.
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عدد المساهمات : 542
تاريخ التسجيل : 16/06/2010

مُساهمةموضوع: رد: مراجع ودوائر وأعطال و شرح صيانة -CRT-LCD -plasma   الجمعة أبريل 22, 2011 3:08 am

LAYOUT INFORMATION HANDLING SYSTEM VARIANCE
BEAM (SWEEP)




General Information


Process obarbotki signals sweep chassis MD1 is controlled by
sweep TDA9151 Integrated Circuit IC401. This programmable controller
sweep (deflection) is placed in the enclosure with dual inline
20-feet.
This processor has high performance synchronization and control
deflection (using DC voltage) is used in television
receivers built as analog and digital principles. This processor
performs the processing functions of horizontal and vertical scanning for all
television standards. ProcessorTDA9151, depending on the frequency
line scan and area of ​​application, may use the frequency sweep
synchronized with the frequency of lines, the value of 6.75, 13.5 or 27 MHz, and requires
a very small number of external components. This device can be programmed
on self-tuning mode. Or install a non-programmable mode with fixed
steepness. The management of these regimes and a significant number of other functions
via bus IIC.

Function Description
For the controller TDA9151 requires a minimum of three signals (except power).
It's the following signals: the clock signal, synchronous with the frequency
lines (LLC) on the leg 14, which comes with a PCB DG (DG-PCB); signal
the pin 12 of integrated circuit IC316 (Buffer clock source);
and IIC bus signals on the legs 17 and 18 (SDA - serial data channel, SCL
- Serial link clock).
No Signal LLC This device is unable to work because the built-in
he logic circuit uses the signal synchronization LLC as the system
clock. Data transmission over the IIC bus is necessary for this to
device could perform the required tasks. From the outset of the integral
scheme uses the input signals HA and VA with legs 13 and 12, respectively,
for the formation of horizontal and vertical trigger pulse. Pulses
HA and VA also comes with PCB DG-PCB.
These signals are output V-Processor at 100 feet (HA) and 99 (VA). If the signals
LLC is absent, the output will be turned off and all work suspended.
As a result, will delay the triggering pulse on line scan
2 ms, the output current E / W (correction of the magnetic field of the earth in an east-
West) is reduced to zero, and the output current vertical refresh will be reduced
by 20% during the period of 100 msec.
Frequency signal LLC, which is fed to the input through the leg 14, arrives at
Pre-scale integrated circuit, which is used to
ensure internal frequency. This internal frequency is used to synchronize
internal processing. Leg 5 (LLLS) is the choice of stem generator
clock synchronous with the frequency line scanning, which is used
Pre-scaling scheme for setting the internal clock frequency
pulses.
Horizontal output
Trigger pulse horizontal scan, which is formed from the momentum
HA, is output from the leg 20. Synchronization of the output pulse is
with a horizontal flyback pulse, which is the input
through pin 1. To help ensure the linearity of the horizontally
electronic tubes 16:9, with 19 feet given impetus to shift the center
(OFCS-Off Center Shift).
Vertical output
outputs of the vertical scanning (VOUTA and VOUTB) served with a leg 10
and 11 integrated circuit IC401 and together form a differential output
current which is fed to the output of an integrated circuit vertical refresh
IC451, located on the PCB D (D-PCB).
The output signal E / W (correction of the magnetic field of the earth in an east-west)
Signal image geometry E / W, which is issued with a six foot controller deviation
(Integrated circuit IC401) is applied to the leg 12 of the integrated circuit IC451 for
further processing. The value of reference current signal processing geometry
E / W and output vertical refresh coming from the integral
circuit IC401 is given on the leg 8 (RCONV).
If, because of the content of a particular image there are fluctuations in the value
EHT (extra voltage flyback), it can also arise, and fluctuations
in the geometry of the image. However, to control the value of the EHT through the channel 150V
used input pins 7 (EHT). If there are any changes, the output
Signal E / W is configured in such a way as to ensure optimum geometry
image.
The input signal protection
Input pin 3 signals protection (PROT), a signal which is given by
Resistors R413 and R415, separated from the signal EHT. receives a voltage which is
in case of exceeding the value of 3.9 disables the output of the horizontal
sweep. The deviation of the beam is suspended, the current E / W decreases
to zero. and the output current of the vertical scanning is reduced by 20%.


OUTPUT HORIZONTAL SWEEP


Impulses controlling the frequency of line scanning for the cascade triggering pulse
Horizontal comes with 20 feet of the controller deflection system
with the value in the full sweep of 1c and pass through the condenser S506. Diode D508
provides a quick discharge of the capacitor C506 in the phase locking of the transistor
Q502. From the scheme of the cascade row buffer, as well as from the circuit output of the generator
triggering pulse can be clearly seen that this cascade control current with
low impedance. This cascade triggering pulse is able to provide the requested
controlling the base current of up to 0.9 amps for transformer triggering pulse
(Turns ratio 7:1) output stage. To limit the inductive
peaks during the interruption phase locking in parallel with the primary winding of the transformer
T502 included RC-chain consisting of resistors R524, R528 and capacitor
C507. Cascade trigger pulse operates in antiphase with respect to the output
cascade. That is, at a time when transistor Q504 is in a state of conduction.


[ندعوك للتسجيل في المنتدى أو التعريف بنفسك لمعاينة هذه الصورة]
Figure 1

OUTPUT VERTICAL SWEEP


Scheme TDA8350Q is a scheme of power, which is used in
deviation from the refresh rate from 50 to 120 Hz and a frequency of horizontal
scan range ot15 to 64 kHz. This circuit generates an output signal of the vertical
scan, which is controlled by DC. In addition, it is composed of
Driver "East-West" (raster image correction resulting from the influence of
magnetic fields in the east-west direction) for the suppression of the current of the diode modulator.
To start the vertical scanning circuit controller deflection produces the output
differential (difference) current which is fed to the legs 1 and 2, the integral
circuit IC451 (TDA8350Q), where between the input points included a resistor R451. Resistor
R451 is used to determine the output current through the coil of deflection. Itself
scheme zepuskayuschego momentum in the vertical is a scheme of the bridge type. Coil
deviation, which is included between the input amplifiers on legs 3 and 9, is
operate in opposite directions. External resistors R452, R453 are connected in series
and provide feedback information, which is fed to the input through the leg
3. Management of a differential input circuit by the voltage.
Flyback voltage is set using the external power supply. This additional
power is supplied through the stem 8 and is valid for a period obtatnogo stroke.
Voltage VFB, which exists on the coil as the voltage return
turn, can serve as supplementary food by eliminating the decoupling
capacitor. This input stage has a complete defense, namely: ·

  • Overtemperature protection
  • Protection against short circuit between the legs 5 and 9.
  • Protection against short-circuit output pins supply (VP) and ground (GND).


Protection scheme VO (guard) is provided through the leg 10. Protection circuit is activated
under the following conditions:

  • During the flyback
  • During a short circuit coil and during short-circuit output
    pins 5 and 9 on the findings of VP and GND.
  • During the emergence of an open circuit.
  • In the case where the activated temperature protection.




SCHEME DAF (DYNAMIC FOCUS astigmatism correction)


General description
DAF scheme consists of an electron gun DAF + Scheme of dynamic focusing.
It is intended to remedy the deterioration of focus that accompanies
the emergence of "astigmatism", as well as in CRT, which has a slope
plane of the tube.
With this scheme can achieve a good image for the fall
screen resolution for every nooks and corners and re-establish
image pritushennogo screen.
The need for the scheme DAF

  1. The phenomenon of astigmatism
    In general, the image on the CRT screen is obtained in that spot beam, which
    This electron beam emitted from an electron gun, leaves, striking
    of phosphorus. This base (substrate) and forms a spot beam. This glow persists
    on the screen and turns up, down and sideways when performing work
    deflection system. Astigmatism occurs at the base (substrate) in the spot beam
    during operations deviation. With regard to the phenomenon of astigmatism, the
    because it caused a lowering of image resolution, it became necessary
    review and further investigate this phenomenon.
  2. Revision of the phenomenon of astigmatism
    The chassis MD1 as an internal element, use the CRT, which is
    "Electron gun DAF". Focal pole of the electron gun DAF (G3)
    consists of two elements (paragraphs). In order to reduce the occurrence of
    astigmatism, the device (gun) is made in the form of cracks.
  3. Deterioration of the focusing, which is accompanied by obtaining a flat screen
    In general, the beam that is emitted from an electron gun configured
    to focus the image with the pole (point) focus. When the screen is on
    form close to the plane, there is a difference in the position of the focus beam
    in the central part of the image and on the periphery of the screen.


Scheme of dynamic focusing
In conventional CRT beam is focused at the focal point, obtained by applying
constant voltage DC. It is applied as the anode
tension. for a period of minutes to 1 / 4 - 1 / 3 as the focal stress.

However, the distance that must pass an electron beam of the CRT is different in the central
of the screen and in its peripheral parts, so even if
for the central part of the screen is obtained the best focusing, in the neighboring parts
screen will be observed violation of focus. The problem of deteriorating focus particularly
strong effect on the periphery of the screen.
Acceptance of the concept of the dynamic focus
The chassis MD1 to CRT is applied additional stress focusing, due to
which realized the concept of "dynamic change of focus."
Thanks to this improvement is focusing on the periphery of the screen.

The current scheme
This scheme creates a wave of parabolic shape, which corresponds to the irregularity
focal stress. Vertical and horizontal pulses are formed when
using integrated circuit IC701, which is located on the PCB H.
Then, with the help of the integrated circuit, creating a parabolic wave
signal.

  1. Vertical parabolic wave signal
    Vertical sawtooth wave signal comes from the legs 21 integral
    circuit IC701, located on the PCB H. Then the integrated circuit
    Q705 passes to the regime of a parabolic wave. Then, this signal is amplified
    transistors Q710, Q711, and these signals are added to the signal on the leg 4
    transformer T701.
  2. Horizontal parabolic wave signal
    Horizontal momentum leaves with three legs of the integrated circuit IC701. He then
    enhanced transistors Q704, Q706 and fed to transistor Q707. After
    of the LC-circuit connected to the transistor Q707, (built in) goes to
    mode of the parabolic wave. Variable similarly parabolic wave
    served on the leg 1 - 2 of transformer T701.
  3. Synthesis - output parabolic wave
    Horizontal and vertical parabolic waves together on the transformer
    T701. Then synthesize the parabolic wave comes from the transformer
    T701 and through the condenser is fed to the line transformer (FBT) and the sum
    with focal pole CRT. Thus, when moving from the center of the screen to
    its periphery in order to obtain optimum focus, focal stress
    increases.
    In the observation of focal stress that passes through the screen surface, it
    is at the intersection points close to the same parabolic several
    folded shape. Scheme of dynamic focusing is a scheme which
    exactly with the above-mentioned parabolic method modulates focal
    voltage according to the scanning electron beam.



SETTING GEOMETRY IMAGES


In TVs CRT format 16: 9 is required additional circuit, which
used to adjust the image geometry. This additional circuit is used
in order to suppress the influence of Earth's magnetic field.
On the chassis MD1, this scheme is implemented as an integrated circuit IC4801, which
contains two operational amplifiers. These operational amplifiers are formed
as a scheme Outlet.
IC4801 integrated circuit powered by direct current.
The user can adjust the amount of this current mode OSD (on screen display
TV).
The user can configure the geometry of the image in 32 steps (+16 / -16).
As the value in OSD mode output DC to 19 feet of the integral
circuit controller IC401 deviation increases and becomes positive.
This current is applied to the legs of 3 and 6 of the integrated circuit IC4801.
At the foot 3 is fed inverted input signal from the integrated operational amplifier
1, and the input 6 is fed through a leg does not invert the input signal is operational
amplifier 2.
As a result of increasing direct current (DC) inverted input
operational amplifier 1 must reduce its output and the output
signal of operational amplifier 2 is enhanced by increasing its output. Result
these operations is to rotate the image clockwise. Similarly,
way, when a constant current (DC) decreases, the output signal from the operating
amplifier 1 is enhanced by increasing its output and the output of the operational
amplifier 2 decreases. The result of these operations is the image rotation
counterclockwise.
الرجوع الى أعلى الصفحة اذهب الى الأسفل
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عدد المساهمات : 542
تاريخ التسجيل : 16/06/2010

مُساهمةموضوع: رد: مراجع ودوائر وأعطال و شرح صيانة -CRT-LCD -plasma   الجمعة أبريل 22, 2011 3:09 am

LAYOUT INFORMATION HANDLING SYSTEM VARIANCE
BEAM (SWEEP)




General Information


Process obarbotki signals sweep chassis MD1 is controlled by
sweep TDA9151 Integrated Circuit IC401. This programmable controller
sweep (deflection) is placed in the enclosure with dual inline
20-feet.
This processor has high performance synchronization and control
deflection (using DC voltage) is used in television
receivers built as analog and digital principles. This processor
performs the processing functions of horizontal and vertical scanning for all
television standards. ProcessorTDA9151, depending on the frequency
line scan and area of ​​application, may use the frequency sweep
synchronized with the frequency of lines, the value of 6.75, 13.5 or 27 MHz, and requires
a very small number of external components. This device can be programmed
on self-tuning mode. Or install a non-programmable mode with fixed
steepness. The management of these regimes and a significant number of other functions
via bus IIC.

Function Description
For the controller TDA9151 requires a minimum of three signals (except power).
It's the following signals: the clock signal, synchronous with the frequency
lines (LLC) on the leg 14, which comes with a PCB DG (DG-PCB); signal
the pin 12 of integrated circuit IC316 (Buffer clock source);
and IIC bus signals on the legs 17 and 18 (SDA - serial data channel, SCL
- Serial link clock).
No Signal LLC This device is unable to work because the built-in
he logic circuit uses the signal synchronization LLC as the system
clock. Data transmission over the IIC bus is necessary for this to
device could perform the required tasks. From the outset of the integral
scheme uses the input signals HA and VA with legs 13 and 12, respectively,
for the formation of horizontal and vertical trigger pulse. Pulses
HA and VA also comes with PCB DG-PCB.
These signals are output V-Processor at 100 feet (HA) and 99 (VA). If the signals
LLC is absent, the output will be turned off and all work suspended.
As a result, will delay the triggering pulse on line scan
2 ms, the output current E / W (correction of the magnetic field of the earth in an east-
West) is reduced to zero, and the output current vertical refresh will be reduced
by 20% during the period of 100 msec.
Frequency signal LLC, which is fed to the input through the leg 14, arrives at
Pre-scale integrated circuit, which is used to
ensure internal frequency. This internal frequency is used to synchronize
internal processing. Leg 5 (LLLS) is the choice of stem generator
clock synchronous with the frequency line scanning, which is used
Pre-scaling scheme for setting the internal clock frequency
pulses.
Horizontal output
Trigger pulse horizontal scan, which is formed from the momentum
HA, is output from the leg 20. Synchronization of the output pulse is
with a horizontal flyback pulse, which is the input
through pin 1. To help ensure the linearity of the horizontally
electronic tubes 16:9, with 19 feet given impetus to shift the center
(OFCS-Off Center Shift).
Vertical output
outputs of the vertical scanning (VOUTA and VOUTB) served with a leg 10
and 11 integrated circuit IC401 and together form a differential output
current which is fed to the output of an integrated circuit vertical refresh
IC451, located on the PCB D (D-PCB).
The output signal E / W (correction of the magnetic field of the earth in an east-west)
Signal image geometry E / W, which is issued with a six foot controller deviation
(Integrated circuit IC401) is applied to the leg 12 of the integrated circuit IC451 for
further processing. The value of reference current signal processing geometry
E / W and output vertical refresh coming from the integral
circuit IC401 is given on the leg 8 (RCONV).
If, because of the content of a particular image there are fluctuations in the value
EHT (extra voltage flyback), it can also arise, and fluctuations
in the geometry of the image. However, to control the value of the EHT through the channel 150V
used input pins 7 (EHT). If there are any changes, the output
Signal E / W is configured in such a way as to ensure optimum geometry
image.
The input signal protection
Input pin 3 signals protection (PROT), a signal which is given by
Resistors R413 and R415, separated from the signal EHT. receives a voltage which is
in case of exceeding the value of 3.9 disables the output of the horizontal
sweep. The deviation of the beam is suspended, the current E / W decreases
to zero. and the output current of the vertical scanning is reduced by 20%.


OUTPUT HORIZONTAL SWEEP


Impulses controlling the frequency of line scanning for the cascade triggering pulse
Horizontal comes with 20 feet of the controller deflection system
with the value in the full sweep of 1c and pass through the condenser S506. Diode D508
provides a quick discharge of the capacitor C506 in the phase locking of the transistor
Q502. From the scheme of the cascade row buffer, as well as from the circuit output of the generator
triggering pulse can be clearly seen that this cascade control current with
low impedance. This cascade triggering pulse is able to provide the requested
controlling the base current of up to 0.9 amps for transformer triggering pulse
(Turns ratio 7:1) output stage. To limit the inductive
peaks during the interruption phase locking in parallel with the primary winding of the transformer
T502 included RC-chain consisting of resistors R524, R528 and capacitor
C507. Cascade trigger pulse operates in antiphase with respect to the output
cascade. That is, at a time when transistor Q504 is in a state of conduction.


[ندعوك للتسجيل في المنتدى أو التعريف بنفسك لمعاينة هذه الصورة]
Figure 1

OUTPUT VERTICAL SWEEP


Scheme TDA8350Q is a scheme of power, which is used in
deviation from the refresh rate from 50 to 120 Hz and a frequency of horizontal
scan range ot15 to 64 kHz. This circuit generates an output signal of the vertical
scan, which is controlled by DC. In addition, it is composed of
Driver "East-West" (raster image correction resulting from the influence of
magnetic fields in the east-west direction) for the suppression of the current of the diode modulator.
To start the vertical scanning circuit controller deflection produces the output
differential (difference) current which is fed to the legs 1 and 2, the integral
circuit IC451 (TDA8350Q), where between the input points included a resistor R451. Resistor
R451 is used to determine the output current through the coil of deflection. Itself
scheme zepuskayuschego momentum in the vertical is a scheme of the bridge type. Coil
deviation, which is included between the input amplifiers on legs 3 and 9, is
operate in opposite directions. External resistors R452, R453 are connected in series
and provide feedback information, which is fed to the input through the leg
3. Management of a differential input circuit by the voltage.
Flyback voltage is set using the external power supply. This additional
power is supplied through the stem 8 and is valid for a period obtatnogo stroke.
Voltage VFB, which exists on the coil as the voltage return
turn, can serve as supplementary food by eliminating the decoupling
capacitor. This input stage has a complete defense, namely: ·

  • Overtemperature protection
  • Protection against short circuit between the legs 5 and 9.
  • Protection against short-circuit output pins supply (VP) and ground (GND).


Protection scheme VO (guard) is provided through the leg 10. Protection circuit is activated
under the following conditions:

  • During the flyback
  • During a short circuit coil and during short-circuit output
    pins 5 and 9 on the findings of VP and GND.
  • During the emergence of an open circuit.
  • In the case where the activated temperature protection.




SCHEME DAF (DYNAMIC FOCUS astigmatism correction)


General description
DAF scheme consists of an electron gun DAF + Scheme of dynamic focusing.
It is intended to remedy the deterioration of focus that accompanies
the emergence of "astigmatism", as well as in CRT, which has a slope
plane of the tube.
With this scheme can achieve a good image for the fall
screen resolution for every nooks and corners and re-establish
image pritushennogo screen.
The need for the scheme DAF

  1. The phenomenon of astigmatism
    In general, the image on the CRT screen is obtained in that spot beam, which
    This electron beam emitted from an electron gun, leaves, striking
    of phosphorus. This base (substrate) and forms a spot beam. This glow persists
    on the screen and turns up, down and sideways when performing work
    deflection system. Astigmatism occurs at the base (substrate) in the spot beam
    during operations deviation. With regard to the phenomenon of astigmatism, the
    because it caused a lowering of image resolution, it became necessary
    review and further investigate this phenomenon.
  2. Revision of the phenomenon of astigmatism
    The chassis MD1 as an internal element, use the CRT, which is
    "Electron gun DAF". Focal pole of the electron gun DAF (G3)
    consists of two elements (paragraphs). In order to reduce the occurrence of
    astigmatism, the device (gun) is made in the form of cracks.
  3. Deterioration of the focusing, which is accompanied by obtaining a flat screen
    In general, the beam that is emitted from an electron gun configured
    to focus the image with the pole (point) focus. When the screen is on
    form close to the plane, there is a difference in the position of the focus beam
    in the central part of the image and on the periphery of the screen.


Scheme of dynamic focusing
In conventional CRT beam is focused at the focal point, obtained by applying
constant voltage DC. It is applied as the anode
tension. for a period of minutes to 1 / 4 - 1 / 3 as the focal stress.

However, the distance that must pass an electron beam of the CRT is different in the central
of the screen and in its peripheral parts, so even if
for the central part of the screen is obtained the best focusing, in the neighboring parts
screen will be observed violation of focus. The problem of deteriorating focus particularly
strong effect on the periphery of the screen.
Acceptance of the concept of the dynamic focus
The chassis MD1 to CRT is applied additional stress focusing, due to
which realized the concept of "dynamic change of focus."
Thanks to this improvement is focusing on the periphery of the screen.

The current scheme
This scheme creates a wave of parabolic shape, which corresponds to the irregularity
focal stress. Vertical and horizontal pulses are formed when
using integrated circuit IC701, which is located on the PCB H.
Then, with the help of the integrated circuit, creating a parabolic wave
signal.

  1. Vertical parabolic wave signal
    Vertical sawtooth wave signal comes from the legs 21 integral
    circuit IC701, located on the PCB H. Then the integrated circuit
    Q705 passes to the regime of a parabolic wave. Then, this signal is amplified
    transistors Q710, Q711, and these signals are added to the signal on the leg 4
    transformer T701.
  2. Horizontal parabolic wave signal
    Horizontal momentum leaves with three legs of the integrated circuit IC701. He then
    enhanced transistors Q704, Q706 and fed to transistor Q707. After
    of the LC-circuit connected to the transistor Q707, (built in) goes to
    mode of the parabolic wave. Variable similarly parabolic wave
    served on the leg 1 - 2 of transformer T701.
  3. Synthesis - output parabolic wave
    Horizontal and vertical parabolic waves together on the transformer
    T701. Then synthesize the parabolic wave comes from the transformer
    T701 and through the condenser is fed to the line transformer (FBT) and the sum
    with focal pole CRT. Thus, when moving from the center of the screen to
    its periphery in order to obtain optimum focus, focal stress
    increases.
    In the observation of focal stress that passes through the screen surface, it
    is at the intersection points close to the same parabolic several
    folded shape. Scheme of dynamic focusing is a scheme which
    exactly with the above-mentioned parabolic method modulates focal
    voltage according to the scanning electron beam.



SETTING GEOMETRY IMAGES


In TVs CRT format 16: 9 is required additional circuit, which
used to adjust the image geometry. This additional circuit is used
in order to suppress the influence of Earth's magnetic field.
On the chassis MD1, this scheme is implemented as an integrated circuit IC4801, which
contains two operational amplifiers. These operational amplifiers are formed
as a scheme Outlet.
IC4801 integrated circuit powered by direct current.
The user can adjust the amount of this current mode OSD (on screen display
TV).
The user can configure the geometry of the image in 32 steps (+16 / -16).
As the value in OSD mode output DC to 19 feet of the integral
circuit controller IC401 deviation increases and becomes positive.
This current is applied to the legs of 3 and 6 of the integrated circuit IC4801.
At the foot 3 is fed inverted input signal from the integrated operational amplifier
1, and the input 6 is fed through a leg does not invert the input signal is operational
amplifier 2.
As a result of increasing direct current (DC) inverted input
operational amplifier 1 must reduce its output and the output
signal of operational amplifier 2 is enhanced by increasing its output. Result
these operations is to rotate the image clockwise. Similarly,
way, when a constant current (DC) decreases, the output signal from the operating
amplifier 1 is enhanced by increasing its output and the output of the operational
amplifier 2 decreases. The result of these operations is the image rotation
counterclockwise.
الرجوع الى أعلى الصفحة اذهب الى الأسفل
MSA
مشرف عام
مشرف عام


عدد المساهمات : 542
تاريخ التسجيل : 16/06/2010

مُساهمةموضوع: رد: مراجع ودوائر وأعطال و شرح صيانة -CRT-LCD -plasma   الجمعة أبريل 22, 2011 3:10 am

LAYOUT INFORMATION HANDLING SYSTEM VARIANCE
BEAM (SWEEP)




General Information


Process obarbotki signals sweep chassis MD1 is controlled by
sweep TDA9151 Integrated Circuit IC401. This programmable controller
sweep (deflection) is placed in the enclosure with dual inline
20-feet.
This processor has high performance synchronization and control
deflection (using DC voltage) is used in television
receivers built as analog and digital principles. This processor
performs the processing functions of horizontal and vertical scanning for all
television standards. ProcessorTDA9151, depending on the frequency
line scan and area of ​​application, may use the frequency sweep
synchronized with the frequency of lines, the value of 6.75, 13.5 or 27 MHz, and requires
a very small number of external components. This device can be programmed
on self-tuning mode. Or install a non-programmable mode with fixed
steepness. The management of these regimes and a significant number of other functions
via bus IIC.

Function Description
For the controller TDA9151 requires a minimum of three signals (except power).
It's the following signals: the clock signal, synchronous with the frequency
lines (LLC) on the leg 14, which comes with a PCB DG (DG-PCB); signal
the pin 12 of integrated circuit IC316 (Buffer clock source);
and IIC bus signals on the legs 17 and 18 (SDA - serial data channel, SCL
- Serial link clock).
No Signal LLC This device is unable to work because the built-in
he logic circuit uses the signal synchronization LLC as the system
clock. Data transmission over the IIC bus is necessary for this to
device could perform the required tasks. From the outset of the integral
scheme uses the input signals HA and VA with legs 13 and 12, respectively,
for the formation of horizontal and vertical trigger pulse. Pulses
HA and VA also comes with PCB DG-PCB.
These signals are output V-Processor at 100 feet (HA) and 99 (VA). If the signals
LLC is absent, the output will be turned off and all work suspended.
As a result, will delay the triggering pulse on line scan
2 ms, the output current E / W (correction of the magnetic field of the earth in an east-
West) is reduced to zero, and the output current vertical refresh will be reduced
by 20% during the period of 100 msec.
Frequency signal LLC, which is fed to the input through the leg 14, arrives at
Pre-scale integrated circuit, which is used to
ensure internal frequency. This internal frequency is used to synchronize
internal processing. Leg 5 (LLLS) is the choice of stem generator
clock synchronous with the frequency line scanning, which is used
Pre-scaling scheme for setting the internal clock frequency
pulses.
Horizontal output
Trigger pulse horizontal scan, which is formed from the momentum
HA, is output from the leg 20. Synchronization of the output pulse is
with a horizontal flyback pulse, which is the input
through pin 1. To help ensure the linearity of the horizontally
electronic tubes 16:9, with 19 feet given impetus to shift the center
(OFCS-Off Center Shift).
Vertical output
outputs of the vertical scanning (VOUTA and VOUTB) served with a leg 10
and 11 integrated circuit IC401 and together form a differential output
current which is fed to the output of an integrated circuit vertical refresh
IC451, located on the PCB D (D-PCB).
The output signal E / W (correction of the magnetic field of the earth in an east-west)
Signal image geometry E / W, which is issued with a six foot controller deviation
(Integrated circuit IC401) is applied to the leg 12 of the integrated circuit IC451 for
further processing. The value of reference current signal processing geometry
E / W and output vertical refresh coming from the integral
circuit IC401 is given on the leg 8 (RCONV).
If, because of the content of a particular image there are fluctuations in the value
EHT (extra voltage flyback), it can also arise, and fluctuations
in the geometry of the image. However, to control the value of the EHT through the channel 150V
used input pins 7 (EHT). If there are any changes, the output
Signal E / W is configured in such a way as to ensure optimum geometry
image.
The input signal protection
Input pin 3 signals protection (PROT), a signal which is given by
Resistors R413 and R415, separated from the signal EHT. receives a voltage which is
in case of exceeding the value of 3.9 disables the output of the horizontal
sweep. The deviation of the beam is suspended, the current E / W decreases
to zero. and the output current of the vertical scanning is reduced by 20%.


OUTPUT HORIZONTAL SWEEP


Impulses controlling the frequency of line scanning for the cascade triggering pulse
Horizontal comes with 20 feet of the controller deflection system
with the value in the full sweep of 1c and pass through the condenser S506. Diode D508
provides a quick discharge of the capacitor C506 in the phase locking of the transistor
Q502. From the scheme of the cascade row buffer, as well as from the circuit output of the generator
triggering pulse can be clearly seen that this cascade control current with
low impedance. This cascade triggering pulse is able to provide the requested
controlling the base current of up to 0.9 amps for transformer triggering pulse
(Turns ratio 7:1) output stage. To limit the inductive
peaks during the interruption phase locking in parallel with the primary winding of the transformer
T502 included RC-chain consisting of resistors R524, R528 and capacitor
C507. Cascade trigger pulse operates in antiphase with respect to the output
cascade. That is, at a time when transistor Q504 is in a state of conduction.


[ندعوك للتسجيل في المنتدى أو التعريف بنفسك لمعاينة هذه الصورة]
Figure 1

OUTPUT VERTICAL SWEEP


Scheme TDA8350Q is a scheme of power, which is used in
deviation from the refresh rate from 50 to 120 Hz and a frequency of horizontal
scan range ot15 to 64 kHz. This circuit generates an output signal of the vertical
scan, which is controlled by DC. In addition, it is composed of
Driver "East-West" (raster image correction resulting from the influence of
magnetic fields in the east-west direction) for the suppression of the current of the diode modulator.
To start the vertical scanning circuit controller deflection produces the output
differential (difference) current which is fed to the legs 1 and 2, the integral
circuit IC451 (TDA8350Q), where between the input points included a resistor R451. Resistor
R451 is used to determine the output current through the coil of deflection. Itself
scheme zepuskayuschego momentum in the vertical is a scheme of the bridge type. Coil
deviation, which is included between the input amplifiers on legs 3 and 9, is
operate in opposite directions. External resistors R452, R453 are connected in series
and provide feedback information, which is fed to the input through the leg
3. Management of a differential input circuit by the voltage.
Flyback voltage is set using the external power supply. This additional
power is supplied through the stem 8 and is valid for a period obtatnogo stroke.
Voltage VFB, which exists on the coil as the voltage return
turn, can serve as supplementary food by eliminating the decoupling
capacitor. This input stage has a complete defense, namely: ·

  • Overtemperature protection
  • Protection against short circuit between the legs 5 and 9.
  • Protection against short-circuit output pins supply (VP) and ground (GND).


Protection scheme VO (guard) is provided through the leg 10. Protection circuit is activated
under the following conditions:

  • During the flyback
  • During a short circuit coil and during short-circuit output
    pins 5 and 9 on the findings of VP and GND.
  • During the emergence of an open circuit.
  • In the case where the activated temperature protection.




SCHEME DAF (DYNAMIC FOCUS astigmatism correction)


General description
DAF scheme consists of an electron gun DAF + Scheme of dynamic focusing.
It is intended to remedy the deterioration of focus that accompanies
the emergence of "astigmatism", as well as in CRT, which has a slope
plane of the tube.
With this scheme can achieve a good image for the fall
screen resolution for every nooks and corners and re-establish
image pritushennogo screen.
The need for the scheme DAF

  1. The phenomenon of astigmatism
    In general, the image on the CRT screen is obtained in that spot beam, which
    This electron beam emitted from an electron gun, leaves, striking
    of phosphorus. This base (substrate) and forms a spot beam. This glow persists
    on the screen and turns up, down and sideways when performing work
    deflection system. Astigmatism occurs at the base (substrate) in the spot beam
    during operations deviation. With regard to the phenomenon of astigmatism, the
    because it caused a lowering of image resolution, it became necessary
    review and further investigate this phenomenon.
  2. Revision of the phenomenon of astigmatism
    The chassis MD1 as an internal element, use the CRT, which is
    "Electron gun DAF". Focal pole of the electron gun DAF (G3)
    consists of two elements (paragraphs). In order to reduce the occurrence of
    astigmatism, the device (gun) is made in the form of cracks.
  3. Deterioration of the focusing, which is accompanied by obtaining a flat screen
    In general, the beam that is emitted from an electron gun configured
    to focus the image with the pole (point) focus. When the screen is on
    form close to the plane, there is a difference in the position of the focus beam
    in the central part of the image and on the periphery of the screen.


Scheme of dynamic focusing
In conventional CRT beam is focused at the focal point, obtained by applying
constant voltage DC. It is applied as the anode
tension. for a period of minutes to 1 / 4 - 1 / 3 as the focal stress.

However, the distance that must pass an electron beam of the CRT is different in the central
of the screen and in its peripheral parts, so even if
for the central part of the screen is obtained the best focusing, in the neighboring parts
screen will be observed violation of focus. The problem of deteriorating focus particularly
strong effect on the periphery of the screen.
Acceptance of the concept of the dynamic focus
The chassis MD1 to CRT is applied additional stress focusing, due to
which realized the concept of "dynamic change of focus."
Thanks to this improvement is focusing on the periphery of the screen.

The current scheme
This scheme creates a wave of parabolic shape, which corresponds to the irregularity
focal stress. Vertical and horizontal pulses are formed when
using integrated circuit IC701, which is located on the PCB H.
Then, with the help of the integrated circuit, creating a parabolic wave
signal.

  1. Vertical parabolic wave signal
    Vertical sawtooth wave signal comes from the legs 21 integral
    circuit IC701, located on the PCB H. Then the integrated circuit
    Q705 passes to the regime of a parabolic wave. Then, this signal is amplified
    transistors Q710, Q711, and these signals are added to the signal on the leg 4
    transformer T701.
  2. Horizontal parabolic wave signal
    Horizontal momentum leaves with three legs of the integrated circuit IC701. He then
    enhanced transistors Q704, Q706 and fed to transistor Q707. After
    of the LC-circuit connected to the transistor Q707, (built in) goes to
    mode of the parabolic wave. Variable similarly parabolic wave
    served on the leg 1 - 2 of transformer T701.
  3. Synthesis - output parabolic wave
    Horizontal and vertical parabolic waves together on the transformer
    T701. Then synthesize the parabolic wave comes from the transformer
    T701 and through the condenser is fed to the line transformer (FBT) and the sum
    with focal pole CRT. Thus, when moving from the center of the screen to
    its periphery in order to obtain optimum focus, focal stress
    increases.
    In the observation of focal stress that passes through the screen surface, it
    is at the intersection points close to the same parabolic several
    folded shape. Scheme of dynamic focusing is a scheme which
    exactly with the above-mentioned parabolic method modulates focal
    voltage according to the scanning electron beam.



SETTING GEOMETRY IMAGES


In TVs CRT format 16: 9 is required additional circuit, which
used to adjust the image geometry. This additional circuit is used
in order to suppress the influence of Earth's magnetic field.
On the chassis MD1, this scheme is implemented as an integrated circuit IC4801, which
contains two operational amplifiers. These operational amplifiers are formed
as a scheme Outlet.
IC4801 integrated circuit powered by direct current.
The user can adjust the amount of this current mode OSD (on screen display
TV).
The user can configure the geometry of the image in 32 steps (+16 / -16).
As the value in OSD mode output DC to 19 feet of the integral
circuit controller IC401 deviation increases and becomes positive.
This current is applied to the legs of 3 and 6 of the integrated circuit IC4801.
At the foot 3 is fed inverted input signal from the integrated operational amplifier
1, and the input 6 is fed through a leg does not invert the input signal is operational
amplifier 2.
As a result of increasing direct current (DC) inverted input
operational amplifier 1 must reduce its output and the output
signal of operational amplifier 2 is enhanced by increasing its output. Result
these operations is to rotate the image clockwise. Similarly,
way, when a constant current (DC) decreases, the output signal from the operating
amplifier 1 is enhanced by increasing its output and the output of the operational
amplifier 2 decreases. The result of these operations is the image rotation
counterclockwise.
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Microprocessor unit (MPU)


General description


MPU unit generates signals for switching and control circuits that are installed on
chassis MX5. It is designed to switch these schemes and their management in accordance
with teams coming from a transmitter remote control, or with the built-in
in the TV control scheme. MPU unit represents one chip in the form of supplements
MOS structure, which contains a ROM (read-only memory) capacity
16 KB and sign generator that allows you to simultaneously display eight
colors.
Key Features

  1. Decode the signals coming in the form of coded signals from the remote
    Control (carrier frequency: 36.7 kHz).
  2. Setting the voltage generator and storage 100 positions.
  3. Additional duplication of information.
    Keeping in integrated circuit memory (IC1102) setting data, switching
    schemes of control and configuration information and reading them out.
  4. Enforcement of a "display on the TV screen."
    Issuance of GLC signals (RGB) for communications mode display on screen "
    (OSD) for playback on a CRT.
  5. Switching and control.
    Issuance of control signals for picture and sound. For example, to switch
    mode TV / AV (TV / AV).
  6. Customize
    Issuance of values ​​for the levels set for the scheme VCJ / VIF ("videohromaticheskie
    Jungle "/" Intermediate Frequency Video ") (IC601) through
    bus IIC.
  7. Implementation of the interface with the scheme Teletext.


MPU unit administers the scheme through Teletext bus IIC.

[ندعوك للتسجيل في المنتدى أو التعريف بنفسك لمعاينة هذه الصورة]
Figure 1

  1. IIC bus is a system of two buses, consisting of a data channel
    and the channel clock.
  2. This bus allows the chassis MH5 large number of switching
    and control functions.

The microprocessor MPU IC1101 on the integrated circuit generates bus signals IIC,
that govern the technical support of the following configuration.

  1. EEPROM (electronically erasable programmable read only memory)
    IC IC1101 (24C04AIPA21 or S-24C04ADP).

    This memory is a nonvolatile memory blocks with 4 Kbyte
    performed on the microchip and the scheme of SEIKO. Both have a bit of memory configuration
    512 x 8 bits.
  2. Scheme VCJ / VIF ("Videohromaticheskie Jungle" / "intermediate
    Video Frequency ")
    (M52770SP).

    IC VIF / VCJ is controlled by the bus IIC. The functions that
    can be controlled externally, include the following: COLOR (color), NTSC-TINT (predominant
    color tone of NTSC), BRIGHT (brightness), CONTRAST (contrast), SHARPNESS
    (Sharpness), H-CENTER (center horizontal), CUT-OFF (blocking, cutoff)
    DRIVE (leading pulse), COLOR SYSTEM (Broadcast System), etc.
  3. IC TEXT (TEXT) (CF70204).
    IC TEXT decodes Teletext information,
    carrier for which a row of vertical blanking
    sweep.

The integrated circuit memory



[ندعوك للتسجيل في المنتدى أو التعريف بنفسك لمعاينة هذه الصورة]
Figure 2
The scheme memory IC1102 receives information listed below, which comes
through the IIC bus with a scheme microprocessor MPU IC1101. These data are input
or output, depending on what is needed. Further, since this integral
scheme is a scheme of non-volatile memory type, the data stored on it
permanently even if power is off.

Table 1
Number of legs
Name of the legsFunction
1 A0Address land chip
2A1 Address land chip
3A2Address land chip
4VSSLand
5 SDASerial data channel (input / output)
6SCLSerial link clock (input / output)
7WPLand
8VDDFood + 5c


Recent memory.
These memories contain the following information to be stored
in memory, even when the power supply stops and stops
work EEPROM.



  1. Information about the voltage W in the range (VL, VH, U) 100
    channels.
  2. Information for the AFC (Automatic Frequency Control)
    SKIP (skip), COLOUR SYSTEM (Broadcast System) and SIF (intermediate
    frequency audio signal) to 100 channels.
  3. The last cell for each switching mode.
  4. Data volume.
  5. Mode of TV / AV (TV / AV).
  6. Selecting ON / OFF (ON / OFF).
  7. Set the timer and auto power off.
  8. Setting maintenance mode.
  9. Data Color, NTSC TINT (the predominant hue
    System NTSC, BRIGHT (brightness), CONTRAST (contrast), as well as data
    controller digital-analog (DAC) SHARPNESS (sharpness), and each of the elements
    DAC data for the embedded images: TONE (Tone), RGB-CUT OFF (cutoff
    GLC), RGB-DRIVE (leading pulse GLC), etc.
  10. PICTURE menu
  11. CHANEL COLOUR SET (Set color channel) for each channel.
  12. CHILD LOCK (lock child records) for each channel.


Scheme cusp (reset) to the initial state
During the execution of operations on / off (on / off) the power, either in
time instant the voltage drop in the channel + B, the circuit microprocessor MPU
IC1101 filed under voltage. In this case, it is likely incorrect
of the microprocessor MPU.
In order to prevent malfunction the microprocessor, this scheme
activates the momentum back, which is served up until the voltage
MPU power is normal.
When you turn the power switch in the case when the voltage VDD to the voltage
VCC scheme MPU, applied to the integrated circuit is less than 4.5 in IC1103, the voltage
to pin 1 of integrated circuit IC1103 remains low (LOW) and the scheme
MPU returns to its original state.
MPU scheme starts to work again when the voltage VDD becomes 4,5.

OPTIONS


Color System

Table 2
Address the EEPROMSoftware code
(Hex)
Color system for TV (television)Color system for AV (audio video)
X'0FA '
0HPAL / SECAM / NTSC 4.43/NTSC 3.58PAL / SECAM / NTSC 4.43/NTSC 3.58
1HPAL / NTSC 4.43 / NTSC 3.58PAL / NTSC 4.43 / NTSC 3.58
2HPAL / NTSC 3.58PAL / NTSC 3.58
3HPAL / NTSC 4.43PAL / NTSC 4.43 / NTSC 3.58
4HPAL / NTSC 4.43PAL / NTSC 4.43
5HPAL / SECAM / NTSC 4.43PAL / SECAM / NTSC 4.43
6HPAL / SECAM / NTSC 4.43PAL / SECAM / NTSC 4.43/NTSC 3.58
SOUND SYSTEM

Table 3
EEPROM addressSoftware code (hex)Intermediate frequency sound signal (MHz)
X'0FA '0H4.5, 5.5, 6.0, 6.5
1H5.5, 6.0, 6.5
2H5.5, 6.5
3H6.0, 6.5
4H5.5
5H4.5, 5.5
SHOW SYSTEM DEMO PANASONIC

Table 4
EEPROM addressSoftware code (hex)Notes
X'0FC 'AAHC DEMO PANASONIC
55HFREE DEMO PANASONIC
TELETEXT (TELETEXT)

Table 5
EEPROM addressSoftware code (hex)Notes
X'0FD 'AAHC TELETEXT
55HNO TELETEXT
SCHEME Muffling NOISE SASO (SURFACE ACTIVE FILTER)

Table 6

AddressSoftware code (hex)Notes
X'0FE 'AAHCo noise jamming scheme SASO
55HWithout the noise jamming scheme SASO
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Muffling NOISE

Table 7
AddressSoftware code (hex)Notes
X'0FF 'AAHC jamming noise
55HWithout jamming noise



FEET OF THE MICROPROCESSOR MPU to integrated circuits



Table 8
Number of legsName IN / OUTFunction
1 REMOTE INP06INInput the remote control
4KEYSCANADIN 2INLog in to the input voltage switching.
0,000-0,433 in: Reduced number of channel
0,797-1,070 in: Increase in number of channel
1,424-1,696 in: Volume Down
2,050-2,323 in: Volume
2,667-2,950 in: Switching TV / AV (TV / AV)
3,304-3,576 in: PRESET (Pre-job)
5AFC INAD1N3INInput voltage circuits AFC (Automatic control
frequency) tuner
64.5/OTHERSADIN4OUT4.5 MHz switching
9AUTO SEARCHADIN7OUTIncrease speed automatic (AUTO) Search
10BAND1ADIN8OUTRange BAND1 (10)Range BAND2 (11)Mode MODE
L (low)L (low)UHF
L (low)H (high)VHF (High)
H (high)L (low)VHF (Low)
11BAND2ADIN9OUTRange BAND1 (10)Range BAND2 (11)Mode MODE
L (low)L (low)UNF
L (low)H (high)VHF (High)
H (high)L (low)VHF (Low)
18SECAM ADJPWM5OUTSetting the discriminator system SECAM
20FA1P46IN
Factory input terminals are used to suspend
constant communication with the MPU block the TV when data is written to
factory from an external control unit MPU in the EEPROM
through the bus IIC. H (high): Communication from the unit MPU TV by
in normal mode L (low): IIC bus communication with the MPU unit suspended
and provide access from the external control unit to the MPU bus IIC.
21AUDIO DEFEATP45OUTOutput signal end audio Hi (high): cessation of
ON Low (Low): cessation OFF
23SIF2P43OUTSound intermediate frequency signal SIF1Sound intermediate frequency signal SIF2Mode (MODE)
L (low)L (low)4.5 MHz
L (low)H (high)5.5 MHz
H (high)L (low)6.0 MHz
H (high)H (high)6.5 MHz
24SIF1P42OUTSound intermediate frequency signal SIF1Sound intermediate frequency signal SIF2Mode
L (low)L (low)-
L (low)H (high)-
H (high)L (low)-
H (high)H (high)-
26POWER ON / OFFP40OUTSignal on and off power (ON / OFF) in the main scheme
Power
Hi (high): ON (enabled)
Low (Low): OFF (standby)
27H. SYNCHSYNCIN
Input signal is a horizontal synchronization mode OSD
(Display screen). When active, is at the low (Low) level.

29BLANKINGVOBOUTThe output signal suppression mode OSD (on screen display)
30BLUEVOW3OUTOutput signal of the blue for the OSD mode
31GREENVOW2OUTThe output green signal for the OSD mode
32REDVOW1OUTThe output signal of red mode OSD
33BT DACPMWOUTImpulse Tues (PWM Pulse Width Modulation) tuner 2
34RESETRESET/P07INInput signal is reset. Front varies
from low (Low) to high (High)
35V SYNCVSYNC / IRQ 1INThe input signal for vertical synchronization mode OSD (Display
on the screen). In the active state at a low level (Low)
37IIC DATAP03OUT / INTerminal I / O signal data bus IIC
38IIC CLOCKP00OUTTerminal output signal clock bus IIC
39VDDVDDIN+ 5c
40OSC1OSC1INConclusion of the generator clock 12 MHz oscillation
41OSC2OSC2OUTConclusion of the generator clock 12 MHz oscillation
42GND--Land
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Setup



[ندعوك للتسجيل في المنتدى أو التعريف بنفسك لمعاينة هذه الصورة]
Figure 1 (Block diagram of the circuit configuration)




  1. Appointment tuner - convert the signals of television broadcasting VHF / UHF
    (Meter range / ultrashort-wave range) in the intermediate signal
    frequency (38.0 MHz).
  2. Antenna to receive TV signal, which is then amplified by the amplifier
    high frequency.
  3. Built-in generator produces oscillations at the fundamental frequency, intended
    for converting the received signal in the mixer to the total signal (intermediate
    frequency)
  4. Intermediate frequency signal amplified by transistor Q121, then
    applied to SAW (PAF - surface-active filter) (X120) and applied to the
    integrated circuit IC601.


Table 1
VTU (voltage setting), reverse bias
[ندعوك للتسجيل في المنتدى أو التعريف بنفسك لمعاينة هذه الصورة]

Capacity
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Frequency adjustment
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Table 2
IC1101IC1105
Range BAND1Range BAND2BLBHBU
VLL (low)H (high)9c00
VHH (high)L (low)H (high)9c0
VUL (low)L (low)009c


  1. Voltage VT, formed by the controller DAC (digital-analog) unit MPU (pulse-width
    modulation) is applied to the tuner via an inverter Q1180 and smoothing scheme
    PMW. This voltage is applied to the varicap diode, a part of integrated circuit
    vibration generator in block tuner.
  2. IC IC1103, designed to select the range, gives
    voltage signal BL, BH, or BU, depending on changes in the range formed by
    MPU unit as shown in the table.
  3. The scheme of automatic control of high frequency control coefficients
    amplifiers with intermediate and high frequencies. This control is exercised
    so that the amplitude of the output video signal detector is
    constant, despite changes in the input tuner.


Note:
Varactor or varicap is a diode, which changes the capacitance
and reverse voltage. This capacity varies in the opposite direction
magnitude of reverse bias applied to the tank.

Block diagram of the audio circuits


This integrated circuit with built-in audio gain control circuit
Volume / High tone, designed to enhance the audio signal to be applied to
speaker and volume controls and high tones, by filing with the
MPU block the DC voltage (0 - 5V).

[ندعوك للتسجيل في المنتدى أو التعريف بنفسك لمعاينة هذه الصورة]
Figure 2 (A block diagram of the circuit audio)


Signal flow SECAM Color System


General description

  1. The integrated circuit IC670 is a self-tuning, self-calibrating,
    completely
    integrated decoder system SECAM.
  2. The structure of the integrated circuit includes the HF (high frequency) and LF (low
    frequency) filter, demodulator and identification schemes (signal intensity in the
    integrated circuit is ignored).
  3. This integrated circuit does not need any setup and requires very
    only a limited number of external components.
  4. For the calibration and the formation of two-level pulse-type sand
    Castle, which is designed for strobe extinction and the selection of color
    "Flash" is required reference frequency with very high stability.
  5. During the reverse field sweep calibration filters and demodulator
    uses the reference frequency 4.4336 MHz.


[ندعوك للتسجيل في المنتدى أو التعريف بنفسك لمعاينة هذه الصورة]
Figure 3 (A block diagram of the integrated circuit IC670)
Scheme of passage chrominance SECAM system

  1. Full TV signal goes to the leg 16 of the integrated circuit IC670
    through the LC band pass filter (C678, L675).
  2. On the circuit ACC only has color signal (chrominance signal at a carrier
    frequency plus the signal pulse burst).
  3. Once the level of the chrominance signal locks in a certain
    in the scheme of the ACC level value, the color signal enters the circuit cloche
    filter.
  4. Campanulate (Cloche - Women's hat in the shape of the shell) filter is
    giratorno (gyrator) - capacitive type. Its resonance frequency is governed
    during the scan. This provides precise frequency value
    during calibration.
  5. Separate color signals frequency 4.25 MHz and 4.40 MHz, demodulated
    by demodulation scheme, which is integrated circuit PLL (automatic
    tuning phase).
  6. This demodulator is a demodulator such as PLL (Phaso Locked Loop -
    Automatic phase) that uses reference frequency and kangap
    reference to obtain the desired characteristics of the demodulation.
  7. Low-frequency circuit deemphasis (4,25 MHz and 4.40 MHz) is consistent with the scheme
    PLL. The management of this scheme is carried out by tuning the voltage
    coming from the circuit PLL.
  8. Tuning the elements needed to operate the system SECAM, connected
    to pin 8 of integrated circuit IC670.
  9. Color signal of SECAM is detected by means of identification schemes
    Located on the integrated circuit IC601 SYSTEM.
  10. The scheme carries a digital identification scan incoming signal for
    System SECAM (this applies only to a linear method of identification).
  11. These identification schemes are necessary in order to provide a link with
    integrated circuit IC601. This is necessary to ensure that
    available only output from this decoder in a time when
    identified PAL signal.
  12. If the decoded signal of SECAM. then on the leg of a request is sent
    the inclusion of color (color-on) (no current). If this request signal
    received approval (ie, the signal on pin 1 at the level HIGH - high, so
    PAL system is completely absent), and therefore are included (ON) the following signals:
    color difference output signals - (BY) and - (RY), coming from the impedance
    IC IC601, and output signals from the integrated circuit IC670.
  13. If, within two shots was not decoded any signals of
    SECAM, then the demodulation will be initialized before it will be made
    next attempt in the next period, the duration of two frames.
  14. Depending on the level of logic signal on pin 1 output DC
    current or extinguished, or it may be a signal with high impedance.
  15. Two-level pulse-type "sand-castle" forms required
    blanking period and in addition, a clock pulse to the pulse of digital identity
    on the falling edge of the pulse signal burst.
  16. In order to determine the period of calibration, reverse vertical
    sweep is separated from the horizontal scan flyback.
  17. With the help of the output stage, this signal is separated into color difference
    signals R-Y and B-Y.

Output signal of the GLC (RGB)

  1. Incoming signals RY and BY are received on the legs 54 and 55 sintegralnoy scheme
    IC601, and then fed to the matrix scheme.
  2. Blocks of the matrix scheme R, G and B signals are issued a "red" (red),
    "Green" (green) and "blue" (blue) and the signal Y (luminance).
  3. GLC signals (RGB) mode TV / AV (TV / audio-video) serves on the switching
    circuit TV / TEXT (TV / text) in blocks of R (red), G (green) and B (blue).
  4. GLC signals (RGB) mode for OSD (on screen display) Teletext served
    switched-circuit TV / TEXT (TV / text) in blocks of R (red), G
    (Green) and B (blue).
  5. Current level cutoff, according to the control signal coming
    IIC bus from the microprocessor MPU IC1101, set to the mean (central)
    significance level. GLC signals (RGB) is output from the legs 22, 23 and 24
    integrated circuit IC601.
  6. Color difference signals RY and BY are received on an integrated circuit IC601
    on the legs 54 and 55, pass through fixing scheme, and then pass through the amplifier
    color contrast, which is controlled by a microprocessor MPU via the bus
    IIC.
  7. After fixing the signals RY and BY pass through the circuit matrix of a linear
    conversion, the output of which produces color difference signals RY,
    B-Y and G-Y.
  8. After that, of these signals RY, GY and BY by the luminance signal,
    supplied with fixing scheme Y (brightness) signals generated K.Z.S. (R.G.B.).

The value is called the legs of the decoder SECAM

Table 3
LegCharacter the notationDescription
1 FREF / IDENTinput reference frequency (login identification)
2N.Cnot connected
3VccSupply voltage
4SECAM AdjCustomize SECAM
5N.Cnot connected
6GndLand
7BELL ref Reference signal bell-(BELL) filter
8PLL refReference signal filter PLL
9- (R-Y)Chroma output signal - (RY)
10- (B-Y)Chroma output signal - (BY)
11N.Cnot connected
12N.Cnot connected
13N.Cnot connected
14N.Cnot connected
15SCP ininput pulse of "sand-castle"
16Video inThe video input system SECAM
Scheme of the signals chrominance PAL / NTSC

  1. Full TV signal comes from the legs 47 of the integrated circuit IC601,
    passes through the transistor Q160 and falls on the leg 33 of the integrated circuit IC601.
  2. This composite video signal supplied to a bandpass filter (BPF) with a frequency of 4.43
    MHz and a bandpass filter (BPF) with a frequency of 3.58 MHz.
  3. In the circuit switching PAL / NTSC color signal selection is carried out
    via bus IIC.
  4. At the amplifier circuit ACC only has color signal (carrier signal
    color plus the signal pulse burst).
  5. These signals, after the levels of these signals recorded chrominance
    at certain levels, which provide a definite correlation with the brightness,
    served on the synchronized demodulator signals RY and BY, which are intended
    for demodulation system PAL / NTSC.
  6. Reference signals, which are necessary demodulator PAL / NTSC signals RY
    and BY, formed by local, built-in generator that uses
    quartz oscillators X626 (System PAL) and X625 (system NTSC). They are connected
    to the legs 50 and 41 and are separated by the two schemes, which are intended to shift
    in phase.
  7. This generator is synchronized in phase with the signal burst,
    coming from the amplifier ACC, but when working with a system of NTSC color signal
    Synchronization can be shifted in phase by plus or minus 30 degrees, under
    signal of control hue, which comes on the channel
    IIC bus from the microprocessor MPU.
  8. These color signals demodulated by the frequency of incoming generators
    4,43 VCO voltage controlled or 3,58 VCO, which pass through the circuit
    PAL / NTSC.
  9. Chrominance signal PAL / NTSC system detected an authentication scheme PAL / SECAM.
    Results of detection and the AUTO mode are supplied to the output leg 42 circuits
    demodulator and quenching circuits. This output is available for circuit switching PAL / NTSC / SECAM
    and for other purposes.
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Integrated circuits on a single chip IC601


An overview of the scheme M52770SP


Implemented on a single chip integrated circuit M52770SP is a semiconductor
integrated circuit specifically designed for color televisions.
This circuit has an interface for:
intermediate frequency video signal intermediate frequency audio signal, the signal
chroma signal scan for display on a TV screen and control
bus signals.
All control functions are implemented on serial elements, using the channels of bus
IIC. This circumstance provided an opportunity for computer configuration
and implementation of the fundamental ideas of technological change in production lines
televisions.
This scheme has several built-in filters and delay lines, 1H (1 period
scan), which reduces the amount of external circuitry. In addition, thanks
Application for chroma decoder system SECAM, which does not require adjustment,
This streamlined multi-system can be realized on the board with a very
small area, which is quite acceptable for the worldwide distribution of the chassis.
FEATURES


SECTION VIF (intermediate frequency video)


Amp VIF (VIF Amp)


The scheme, which is used in the amplifier VIF, has a very good linearity.
In addition, there is a fully synchronized scheme of the detector, which
PLL is used for detection of video. All this provides excellent
characteristics of DG, DP, SN and beats.
VCO (voltage-controlled oscillator)


Management VCO coil is carried on the bus. Oscillation frequency can be set
to the reference value by means of special coils, made as a coil.
If you provide a center frequency tuning scheme with AFT (automatic
fine tuning), then you can ask a free operating frequency.

Scheme AFT (automatic fine tuning)


Output signal generated from the AFT voltage circuits APC (automatic
phase adjustment), and therefore requires a broader range of coverage for the scheme
APC. AFT output signal is canceled when unlocked
PLL circuit or a weak signal when the output is a central
tension.
Video output


Detection of the output voltage is 2.2 in the full scope. Detection
video made for both positive and negative for
modulated signal. Video detection scheme works for the orderly
negative modulated signal when the mode circuit AGC (automatic
Gain Control) is set to NEG (negative). And in the case where
mode AGC circuit is set to POS (positive) for the SECAM / L, this scheme
operates as a peak AGC circuit with large time constant. Then the detected
video signal, inverted in the integrated circuit, using the crossing clock
negative polarity.
In the peripheries of SECAM / L requires a sound detector
signal.
SECTION SIF (sound intermediate frequency)


In section detecting FM (frequency modulation) scheme is applied PLL (automatic
tuning phase) for a wide range. This circuit has good linearity
and works with all types of chassis, the carrier frequency for demodulation can be switched
at 4.5 MHz or 6.0 MHz. SIF signals with a frequency of 4.5 MHz, 6.0 MHz and 6.5 MHz can
demodulate mode with carrier frequency 6.0 MHz. You can set
the same level of sound, as in other systems, chassis to get
duplicated the detected output signal in the 4.5 MHz.
VIDEO SECTION


Video output has a value of 1 in the full scope. He arrives at the foot
45 and passes through the following scheme: Switch tv / ext (TV / external)
notch filter chromaticity diagram of Y-DL (delayed luminance signal), the control circuit
image quality. Scheme of the aperture correction DL is designed to improve
performance with respect to emissions, located upstream and downstream
signal. In this scheme, using a delay line for 120 ns (nanoseconds).

COLOUR SECTION


Chrominance signal or video signal is fed to an amplifier AGC (Automatic
adjust color). Then the color signal from the ACC scheme, after the passage of
through a bandpass filter (BPF) of the chrominance signal is fed to the 2-th power. This
signal is processed in the schemes ACC, APC (automatic phase adjustment)
KILLER (damper) and ID (identifier). Setting the carrier frequency notch
BPF filter and automatically. For this purpose the subcarrier
chrominance signal, which is the reference frequency for their work.
AUTOMATIC IDENTIFICATION SYSTEM COLOR TELEVISION


Identification of the color system can be carried out automatically.
It is also possible and manual control. Information on the status (Status) identification
(ID) system can be read using the bus. Signal identification system
SECAM is output to the leg 52.
LOG GLC (RGB IN)


RGB signal input voltage is typically 0.7 in the full scope. Threshold
voltage for FAST BLK is 0,4 to.
CHANGE IN SCP


This output has three threshold levels. 50/60 Hz
Vertical refresh rate is automatically detected and the status of
identification can be considered through the bus. In the absence of input signal frequency
is 50 Hz.
Ramp vertical refresh


Managing a sawtooth vertical deflection signal or switched pulse
through the leg 29. With sawtooth mode amplitude of the output ramp
voltage (signal V-Ramp) is configured using the data consist of 7
bits.
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VIF (Intermediate Frequency VIDEO)


The main function of intermediate frequency section of the video signal is frequency
signal is converted to an intermediate frequency (38,9 MHz / 45.75 MHz) signal
CVBS (composite television signal), which is served later in the section sound
intermediate frequencies to produce sound. In addition, this signal
CVBS is fed into the section color video.
VIF amplifier


VIF input signal from the tuner to the input circuit M52770SP on legs 9 and 10.
VIF amplifier consists of two amplifiers. Gain of the first amplifier
is controlled by the control voltage coming from the IF AGC circuit
(AGC), an intermediate frequency.
Figure 1 shows the relationship between stress IF AGC circuit and the input signal
intermediate frequency.
The first and second amplifier are combined so that the AGC circuit otvatyvala
range 60 dbu (from 50 to 110 dbu dbu). In this case, the output signal from the second
the amplifier is maintained at a constant level of 86 dbu. In accordance with the requirements
put forward by the majority of PAF - filters, input impedance between the legs 9
and 10 is 800 ohms, which included parallel capacitor 5
FSC.

[ندعوك للتسجيل في المنتدى أو التعريف بنفسك لمعاينة هذه الصورة]
Figure 1
Video Detector


In the detector there are two video inputs. - One for video, which
recorded at 86 dbu (56,6 mV in full swing) with
amp VIF. The other - is the input for the signal from the generator,
voltage controlled (VCO). Generator VCO produces fluctuations in the intermediate
frequency (IF). Depending on country-specific intermediate frequency can
have the following meanings: 38.9 MHz (eg, Singapore). 45.75 MHz (eg,
USA) and 58.75 MHz (eg, Japan).
Detector video signal is essentially a frequency multiplier. In addition,
He has two gain stage. At the first stage the output is a signal
at 1B in full swing. The second stage increases to the level of 2.3 in the full
scope. Video output detector is located on the leg 64 circuits M52770SP.
With the help of the software via the built-bus, you can choose a positive
or a negative modulation (POS / NEG).
The output signal on the leg 64 consists of a full TV signal and sound
intermediate frequency signal. This output, after passing through
bandpass filter sound intermediate frequency (SIF BPF), arrives on foot
3 in section sound intermediate frequency and, after passing through the notch
Filter SIF, at the foot section 45 color video.
Synchronism detector fluctuations of


Sync detector detects the condition when the circuit PLL (automatic adjustment
phase) does not work synchronously. This is illustrated in the figure belowFigure 2.
In the case where the PLL circuit operates synchronously, the average DC
current is below the level of 2.75 in. However, when the PLL circuit does not work synchronously
average dc voltage may exceed the reference standard voltage
comparison to 3.3. When this happens, then switch detector synchronization
scheme is activated AFT (automatic fine tuning).
Detector IF AGC (automatic gain control intermediate frequency)


Scheme IF AGC - AGC circuit is a peak (restrictive) type. This peak
AGC circuit compares the level of the top video sync fixed
value of the DC signal. If the amplitude exceeds the reference vertex
level, to reduce the gain on the RF and IF stages fed
appropriate control voltage. Thus, the top clock restored
to the reference level. Peak AGC circuit is also called circuit AGC lock synchronization.
In order to ensure the passage of current charging and discharging during the
circuit AGC, to pin 6 is connected electrolytic capacitor and 0.22
F.
The scheme is also an IF AGC circuit AGC dynamic type. When the level of the detected
output unexpectedly falls, the charge current increases to
speed up circuit AGC. Top sync level detection signal
can be restored for a time equal to approximately 3N (200 us) (3 periods
line scan).

[ندعوك للتسجيل في المنتدى أو التعريف بنفسك لمعاينة هذه الصورة]
Figure 2 (a signal obtained as a result of the circuit PLL)

[ندعوك للتسجيل في المنتدى أو التعريف بنفسك لمعاينة هذه الصورة]
Figure 3 (Block - diagram of RF AGC)
VCO (voltage-controlled oscillator)


VCO coil generator is used to determine that an intermediate frequency (eg,
38.9 MHz, 45.75 MHz, 58.75 MHz), which should produce generator VCO.
AFT (Automatic Fine Tuning)


There are 3 possible types of status signals, whose appearance can be corrected
with the scheme AFT. They are:

  1. weak television signals.
  2. when the PLL circuit does not work synchronously
  3. from the control software on the bus goes canceled
    signal

If an external resistor RAFT, connected to the leg 2 has a sufficiently large
resistance, then u (= b / a) becomes greater.
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Luminance signal


In this part of the manual discusses the treatment of complete television
signal. This signal is primarily divided into two parts, namely, the signal
brightness and color signal. Section brightness or video is only concerned with
processing of the signal Y (luminance). A block diagram of this section in the scheme shown M52770SP
below.


Fixation of input



Brightness and color signals are tied to the leg 45 through a capacitor
capacity of 0,1 and F. The lowest point of complete TV signal (top
clock) is fixed at about 2.2v.

[ندعوك للتسجيل في المنتدى أو التعريف بنفسك لمعاينة هذه الصورة]
Figure 1: Signal for leg 33 (Chrominance signal during the separation of input signals
Y and C)
Switch Video



Managing the switch SW1 is provided from the internal bus
control signal TV / EXT. When the control signal switches to the mode
Television (TV), then establishes contact with the leg 45. On the other hand,
if the control signal to switch the mode EXT, then set
contact with the leg 43. Signals TV IN and EXT IN is a complete television signal
1c value in the full scope.


Switch output signal Y



Switch output signal Y is located on the leg 47. Output
signal from the legs 47 is fed to the legs 48/49 sinhroseparatora and integral
scheme SECAM.


The expansion of black



When a signal expansion of black highlights signal Y (luminance)
Situated in the range 0 - 50 units of brightness IRE - that is, the closer to black
edge of the gray scale of brightness. The transfer function of the expansion is shown in black
Figure 2 This output has its own reference level, fixed
on the value of 3c.

[ندعوك للتسجيل في المنتدى أو التعريف بنفسك لمعاينة هذه الصورة]
Figure 2 (dependence of "Input / Output" extension black)SIF (intermediate frequency audio)


Amplifier-limiter


Carrier frequency sound is fed through an external bandpass filter to the input of the limiter,
this component is removed from the amplitude modulation (AM). Sound carrier
have a frequency of 4.5 MHz, 5.5 MHz, 6.0 MHz and 6.5 MHz. This constraint is
of the 3 stages of amplification. The overall gain of the amplifier-limiter
60 DB.
Detector FM (frequency modulation)


To demodulate the FM signal using a method based management scheme of the phase
PLL. It consists of two parts. The first part - a scheme
APC (automatic adjustment phase), while the second part - is controlled oscillator
voltage (VCO).
Power audio frequency (AF AMP)


Audio frequency amplifier is designed to enhance the demodulated audio
signal. It consists of a filter correction predistortion (Leg 60) in which
fitted with a narrow-band low-pass filter, shown in Figure 1. The composition
circuit includes two resistors R1 and R2, between which you can make a choice, asking
thus different time constants. Information about this is presented in Table 1.
Output voltage of the pin 57 is about 1 in the full scope and level of
DC voltage is equal to approximately 2.5 at.

[ندعوك للتسجيل في المنتدى أو التعريف بنفسك لمعاينة هذه الصورة]

Figure 1 (Audio amplifier with predistortion filter correction.)

Table 1
(The operating parameters of predistortion correction filter at different frequencies inside
carrier.)

Internal carrier frequency (MHz)GainResistanceThe time constant correction circuit (us-ms)
4.5~ 26 dBR1R1 x C = 75
5.5, 6.0, 6,5~ 20 dBR2R2 x C = 50
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Chrominance signal


H.P.F. (Highpass filter) and 1-th power



Color signal arrives at the high-pass filter (HPF), which
has a frequency of 2 MHz locking. This filter removes the signal Y. The greatest value
the gain of the first amplifier chrominance is 25 dB (decibels).
This ratio can be adjusted by means of automatic adjustment
gain (AGC).
Bandpass filter (BPF) chrominance



The function of the notch filter (1 / 2 fsc) is decreasing
gain a point, which is half the carrier frequency. For carrying
equal to 3.58 MHz and 4.43 MHz, these points are set at 1.79 MHz and 2.21 MHz
respectively. The fall performance at half the carrier frequency is set
in such a way as to ensure a quality rejection.
For this bandpass filter can be set two modes, namely, the regime of TV (television)
and mode of EXT (external). In TV mode, the frequency response of filter BPF has
decrease the frequency of the chrominance signal whose magnitude is such as to satisfy
Nyquist slope in the characteristic of PAF - filter. In addition, the frequency reference
color signal is controlled by the automatic adjustment of color schemes.
In EXT mode attenuation is absent.
Gain of the correction amplifier is fixed or in TV mode
in either EXT. In the fixation and is different compared with the value
Managed circuit AGC. However, in the EXT mode, the gain is set
6 dB lower than in the mode of TV.
2-th power



Gain of the 2-th amplifier is approximately
18 dB.
Detector ACC (Automatic Color) Block diagram of the detector ACC
shown in Figure 1 Detector ACC is located in the feedback loop between the 1-m
and 2-m amplifiers. At its input receives the output signal 2 of the amplifier, and output
signal used to control the gain of the first amplifier.
The result is a fixation of the output level of 2-th amplifier.
AGC detector operates only during the outbreak (during color signal synchronization).
It allows you to use the power of the signal flare.

[ندعوك للتسجيل في المنتدى أو التعريف بنفسك لمعاينة هذه الصورة]
Figure 1 (Block diagram of the detector ACC)
VCXO (voltage-controlled crystal oscillator)



The basic frequency of oscillation is provided by crystal oscillators,
are connected to the leg 41 or to the leg 50. Leg 41 is used to connect
oscillator frequency of 3.58 MHz, and the stem 50 to connect the quartz
oscillator frequency 4.43 MHz.
Scheme VCXO not need to configure. Itself acts as a crystal oscillator source
filter and performs internal operations that vyvzyvayut fluctuations scheme
VCXO at the corresponding frequency. The phase adjustment circuit VCXO is executed
with the feedback signal coming from the block of the synthesizer.
Output signal variance on the two routes. One of them is connected via
lowpass filter.
These two signals are combined with the third signal (voltage filter ARS (Automatic
phase adjustment)) on the keyboard. When the output voltage on a block of the synthesizer
increases, increases and phase (creating a phase advance) and vice versa.
In fact, used the carrier to the amplifier input section fluctuations connected
input of another amp. In the amplification of signals sent from the shift
+ - 40 *.
Automatic detection of TV color systems



With the help of the scheme M5277QSP can automatically decide - what kind of system
color television works. The results of the identification system for the system
SECAM are output to the leg 52. It's connected to integrated circuit processing
Signals SECAM, AN5637.
Automatic or manual selection of a system can be set via the bus IIC. For
Manual mode via the IIC bus are defined by crystal oscillator (4.43 / 3.58 MHz) and
system (NTSC / PAL / SECAM).
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SCHEME OF BEAM DEFLECTION



On the following block diagram shows the passage of signals in circuits deviation
beam. Here the signal using the horizontal and vertical synchronizers
divided in order to create clock pulses sweep.
Vertical sync signal is fed to the legs 15 with integrated circuit IC601
on leg 4 of the integrated circuit triggering pulse Vertical IC401.
The integrated circuit IC401 consists of the following: schema trigger pulse
vetrikalnoy sweep, the vertical output circuit and pump circuit. This scheme
serves on the deflection coil vertically sufficient magnitude sawtooth
current for the vertical sweep.
Horizontal sync signal comes from the legs 15 integral
circuit IC601, passes through the circuit triggering pulse on the horizontal transistor
Q549 and then fed to the transformer T550 triggering pulse. This is done
in order to create a big trigger current needed to run the output
horizontal deflection transistor Q551. Transistor Q551 amplifies the signal
Horizontal sync before sending in the scheme of deviation
horizontally.

[ندعوك للتسجيل في المنتدى أو التعريف بنفسك لمعاينة هذه الصورة]
Figure 1 (Scheme deflection in the vertical and horizontal)


Output signal of the horizontal time screwdriver


General description



  1. In order to ensure the immediate inclusion of (ON) and off (OFF)
    Horizontal output circuit, the circuit triggering pulse horizontal
    sweep generates sufficient largest base current (the current trigger pulse)
    and applies it to the output circuit Horizontal (transistor 551),
    as shown in Fig. 2
  2. Output circuit Horizontal plays two roles, namely:

    a) It sends the system deviation (DY) current deviations required to
    In order to ensure that scan the electron beam in the horizontal direction.

    b) Generation of high voltage in the secondary winding of high voltage
    transistor and the flyback supply voltage of the anode electrode
    focusing cathode-ray tubes.


[ندعوك للتسجيل في المنتدى أو التعريف بنفسك لمعاينة هذه الصورة]
Figure 2
The scheme of the signals



  1. Trigger pulse to the horizontal scan leg 15 of the integrated circuit
    IC601 goes to the base tranzistoraQ549, which is a transistor circuit
    zapuskayuschihimpulsov horizontal scan.
  2. In the collector circuit of transistor Q549 has a transformer, which provides
    AC coupling and coupling impedance of the output transistors c
    Horizontal Q551. In order to provide protection from spikes,
    that may arise due to the action back electromotive force (EMF)
    triggering pulse on the transistor (T551), in the scheme introduced by the filter,
    consisting of a resistor R550 and capacitor S548. This filter shunts the emitter
    and a collector of the transistor Q549. Transistor Q551 is the output transistor
    horizontal scan is used to run inline transformer
    with reverse course (T501) and the horizontal deflection coils.
  3. S - correction (non-uniformity in the field) by using a capacitor
    C559, which causes distortion in the upper and lower parts of the signal sweep.
    This distortion is corrected by capacitor C560 and resistor R551.
    Linearity is ensured by an inductance L552 and a resistor R551.
    A diagram of the diode modulator is formed from elements of the D551, D552, C552, C553
    and C550.
  4. Transformer secondary winding line scan shown in T501
    voltage, which is used in different parts of a television receiver:
    for focusing, a CRT, in heaters and nutrition screen, etc.

Work output circuit horiz ontalnoy times screwdriver



  1. The input signal database does not start up until it will not exceed
    a certain value.
  2. At the base of a pulse of positive polarity. As soon as the voltage
    base exceeds a certain level, the transistor Tr is opened. After that,
    collector current 1 increases, and this current begins to flow through the coil of deflection
    (T1 - t2).
  3. If the input signal based on the drops to a certain level, the transistor
    Tr is turned off. The collector current drops to zero, but the coil continues
    current flows. And as long as there is discharge of the resonant capacitor
    With this current gradually decreases, until eventually it reaches zero
    value (t2 - t3).
  4. Then the discharge begins to pass along the contour of 3, passing from the resonant
    capacitor through the coil of deflection. This current flows through a coil of deflection
    in the opposite direction (t3 - t4).
  5. Then, the current deflection coil starts charging a capacitor with the opposite
    characteristics in the resonance chain consisting only of the LC.
  6. However, because of the discharge circuit includes a diode D, the voltage
    contacts between the coil deflection translates the diode conduction state.
    As a result of coil current deviation does not fall into the resonant capacitor
    and the current flowing through the diode discharge. As a result, the phenomenon of resonance is absorbed.
  7. Work scheme is synchronized so that when the diode current reaches 4
    zero, then the base tarnzistora Tr again a pulse of positive polarity
    and everything goes back to the situation described in paragraph 1.
  8. After that, all the work is repeated with steps 2 through 5. Due to this through
    deflection coil regularly runs a sawtooth wave.
  9. Moreover, at this moment, when the transistor Tr is turned off, is generated
    positive impulse voltage flyback, which are larger than,
    than the power supply voltage.
  10. Line transformer with reverse motion uses the momentum back
    speed and generates from it the anode voltage of the CRT, the focal stress and strain
    screen.


Scheme of vertical deviation


General description



  1. The main function of this scheme is to form a sawtooth
    current deviation and increase the vertical ramp signal applied to the coil
    deviations in the vertical for vertical scanning.
  2. Sawtooth signal, which is formed on the integrated circuit IC601,
    comes to integrated circuit IC401 through leg 4 of the scheme. Then this
    sawtooth signal in order to ensure the linearity of the vertical
    compared with the output signals from the output circuit vertical
    sweep.
  3. This signal is then fed to the oscillator ramp, where the integral
    IC601 circuit to switch from 50/60 Hz.
  4. Then, in order to ensure the linearity of the vertical sawtooth
    voltage is compared in the scheme of the triggering pulse Vertical
    with voltage flyback coming from the output circuit vertical sweep.
  5. After that, the ramp signal is amplified and goes to the integrated circuit
    IC401 through the leg 2 on the deflection coil vertically.
  6. Pump circuit with external elements C452, C401 and D401 enhances
    peak sawtooth signal during flyback.
  7. Flyback voltage, supplied from the output circuit vertical sweep
    served on the ramp generator to ensure the sustainability of
    AC and pulse triggering circuit for vertical deflection
    stability of the DC.


The legs of the integrated circuit IC601



Table 1
Number of legsNameDescriptionCondition
1 VIF GNDLegs grounding blocks VIF and SIF0V DC
2 AFT OUTThis leg is the current vyhodom.Vhodnoy impedance 270 Com0.2 to - 8.7 VDC
3LIMITER INStandard input level 100 dBu. Input Impedance 4.7 Com0,5 - 4,5 DC
4RF AGC OUTCurrent output type. Current charging and discharging has a maximum
value of 0,4 mA
0,1 - 8,8 V DC
5QIF OUTOutput pin detector QIF (kvantizirovannoy intermediate
frequency) with a signal SIF FM (frequency-modulated audio intermediate
frequency)
3.2 VDC
6IF AGC filterLegs filter AGC (Auto Gain Control)In 1.9 - 4.6 VDC
7QIF inputInput pin sound carrier QIF (kvantizirovannaya intermediate
frequency)
2.2 VDC
8Spot KillerIn normal operation, an external capacitor is fully charged.
When turning off the power supply that supports a charged capacitor,
for some time, the output RGB (GLC). Retention time
level of this signal depends on the capacity.
7.5 VDC
9VIF INInput impedance is 800 ohms. Capacity - 5 pF.
Notice the agreement with the CFA - the filter.
1,5 V DC
10
11VIF VccThe power supply to block VIF / SIF (intermediate frequency video / en
frequency audio)
5.0 VDC
12FAST BLKManagement switch RGB (GLC) when selecting TV / Half
Tone / EXT (TV / semitone / external)
0,0-0,7 in: Internal signal TV 1,3-3,3 in: External RGB signal
(GLC) in 3,7-5,0: Grayscale
13SCLLeg SCL (serial clock channel bus
IIC)
-
14SCP OUTStem output signal of "sand castle"
[ندعوك للتسجيل في المنتدى أو التعريف بنفسك لمعاينة هذه الصورة]

15H OUTThe output signal pre-launch Horizontal
[ندعوك للتسجيل في المنتدى أو التعريف بنفسك لمعاينة هذه الصورة]

16VSSLeg grounding of logical blocks on the complementary MOS - transistors0V DC
17SDALeg SDA (data channel) bus IIC-
18VDD decouplingVDD voltage to power the logic blocks to complement
MOS - transistors, formed from the triggering voltage Vcc
5VDC
19AFC 1 FILTERLegs filter AFC-1 (automatic frequency control) of the generator
32 fh VCO (voltage controlled)
[ندعوك للتسجيل في المنتدى أو التعريف بنفسك لمعاينة هذه الصورة]

20H OSCLeg generator horizontal vibration0,3-2,45 in DC
21Mute FilterLeg damping filter matches0,0-9,0 VDC
22ROUT GOUT B OUTThese feet belong to the type inference open emitter.
Maximum output current is 4 mA. 1-3,5 in the full sweep of 2-pulse
Reverse 3 - 1H-1period sweep 4-to-ground
[ندعوك للتسجيل في المنتدى أو التعريف بنفسك لمعاينة هذه الصورة]

23
24
25Deflection GndLeg grounding unit deflection 0 in
[ندعوك للتسجيل في المنتدى أو التعريف بنفسك لمعاينة هذه الصورة]

26V OUTStem output clock signal in the vertical
29V RAMP FEEDBACKLeg DC offset to the sawtooth signal
Voltage V-Ramp. Leg detection switch modes Ramp / Pulse
(Saw / pulse)
30V RAMP CThe foot vertical ramp generation with
capacitor C
27Start-up VccControl signal, coming on the bus ICC, to power system
deviation for the output stage VIF / SIF
9.0 VDC
28BIN GIN R INSignal to the input legs of the external RGB with capacitor fixation.
Current charge and discharge is 150mA
2.5 VDC
37
39
31VIDEO / CHROMA VccThe power supply units for video processing and signal
chromaticity
5.0 in
32AFC2 FILTERConnected to the retaining capacitor and load resistor.
Can then be managed horizontal sync phase
scan (H-sync)
4.5 VDC
33CHROMA INFoot, on which a signal via the built-filrt
BPF complete television signal.
3.5 VDC
34ID FILTERFoot filter ID (identification)-
35VIDEO INInput pin video0.6 in the full scope: standard
36X-RAY INProtection against X-ray irradiation0V DC
38BLK HOLDLeg sync black level extension functions
black
-
40CONTRAST CONTFoot filter for detecting ACL-
41X-TALLeg oscillator 3.58
3.3 VDC;
[ندعوك للتسجيل في المنتدى أو التعريف بنفسك لمعاينة هذه الصورة]
70 mV in full swing

42KILLER FILTERFoot filter circuit detection blanking3.7 VDC
43EXT INInput of an external video sync with locking tops1.95 in DC
44CHROMA APC FILTERFoot filter circuit detector APC (Auto
phase)
3.0 VDC
45TV INVideo input tuner (video signal output circuit VIF) with the scheme
fixing the top clock
1.95 in DC
46VCD GNDLeg grounding block processing image signals and chrominance0.0 VDC
47Y SW OUTFoot switch output Y SW (luminance)top sync: 1.3 to complete the television signal: 2c
in full swing
48SYNC SEP INHorizontal sinhroseparator
[ندعوك للتسجيل في المنتدى أو التعريف بنفسك لمعاينة هذه الصورة]

49Vertical sinhroseparator
50X-TAL 4.43Leg of a quartz oscillator (4.43)
3.3 VDC
[ندعوك للتسجيل في المنتدى أو التعريف بنفسك لمعاينة هذه الصورة]
70 mV in full swing

51VIDEO CLAMPCapacitor of the reference signal lock3.0 VDC
52SECAM REFOutput reference signal for SECAM system and detection
SECAM system
PAL / NTSC: 1,4 in
SECAM: 5c
[ندعوك للتسجيل في المنتدى أو التعريف بنفسك لمعاينة هذه الصورة]
approximately 400mV in full swing
53Hi Vcc (9V)The power supply for output stage (trigger pulse RGB (GLC)
output AF (audio frequency) circuits AFT / RF AGC)
9.0 in
54- (B-Y) INChroma input signal - (BY)
[ندعوك للتسجيل في المنتدى أو التعريف بنفسك لمعاينة هذه الصورة]

55- (R-Y) INChroma input signal - (RY)
[ندعوك للتسجيل في المنتدى أو التعريف بنفسك لمعاينة هذه الصورة]

56APC FILTER 2Foot filter circuit detector APC (Auto
phase)
3.0 VDC
57AUDIO OUTStem output settings
2.8 VDC[ندعوك للتسجيل في المنتدى أو التعريف بنفسك لمعاينة هذه الصورة]

58AUDIO BYPASSLeg bypass audioVoltage DC
4.5 MHz: 2.3 to 5.5 MHz: 2.3 to 6.0 MHz: 2.6 to 6.5 MHz: 3.0 in
59EXT AUDIO INLeg external audio input-
60FM DIRECT OUTLeg direct output signal chastotnomodulirovannogo
NTSC: 740 Vrms
PAL: 690 Vrms
2.4 VDC
61VCOLegs VIF1 and VIF2
4.2 VDC[ندعوك للتسجيل في المنتدى أو التعريف بنفسك لمعاينة هذه الصورة]

62
63VIDEO APC FILTER 1The scheme of PLL is configured using an external resistor3.0 VDC
64VIDEO OUTLeg Video Output
[ندعوك للتسجيل في المنتدى أو التعريف بنفسك لمعاينة هذه الصورة]

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مُساهمةموضوع: رد: مراجع ودوائر وأعطال و شرح صيانة -CRT-LCD -plasma   الجمعة أبريل 22, 2011 12:20 pm

SCHEME TELETEXT


Options scheme Teletext


Teletext scheme has the following functions:

  1. Isolation of teletext information from the television signal.
  2. Providing store information in a volume of 4 pages.
  3. Reproduction of teletext pages in the form of a TV image.

Architecture schemes.


The composition schemes include Teletext, basically, 4 chips, each of
which has the following functions:

  1. IC IC3501 (quantizer - delimiter): This scheme
    quantizer - Data Protector performs the following functions: synchronization
    television signal, a selection of information teletext recovery
    clock data from the received video signal. Then the clock signal,
    data and a full sync signals are transmitted to the digital chip detector.
  2. IC IC3502 (decoder): The scheme is designed to decode
    Teletext information. The structure of the decoder includes a block of memory SRAM capacity
    4 pages.
  3. Integrated circuits are IC3503 and IC3506: to switch off
    signal RGB (GLC) to select the Teletext and screen.

The scheme of switching signal RGB (GLC)



  1. Teletext signals R, G, B with IC IC3502 are sent to the legs
    11, 1 and 3 IC IC3506 (analog switch).
  2. Playback signals on the screen of R, G, B with the integrated circuit are sent to IC1101
    on the legs of 11, 1 and 3 IC IC3505 (analog switch).
  3. These signals R, G, B lined up in the TV picture
    (TV / AV - R, G, B) with the help of these switches. Operations on / off
    (ON / OFF) of these switches are performed using the signal damping originating
    with 41 feet of the integrated circuit IC1101.
  4. In the case where the signal (BLK) blanking the screen image coming
    with 41 feet of the integrated circuit IC1101, is high, then the integral
    IC3505 scheme is included. And at the same time, the integrated circuit IC3506 off.
    Therefore, in the case where two characters are simultaneously generated for one
    and the same screen space, a symbol of OSD RGB (on screen display) will have
    precedence over the symbol of teletext.

Protection Scheme


Description of the protection scheme


Function of the protection circuit is to protect the scheme from any danger
in the case of an emergency in the scheme. This scheme prevents the possibility of
causing any harm to the consumer and, in addition, what prevents any
consequences of events that can cause damage to other parts of the circuit.
Protection scheme from X-ray radiation using the front leg 36 integral
IC601 circuit to prevent excess voltage. This scheme provides
protection from too high voltage or from excessive beam current CRT.
If for any reason, the values ​​of high voltage or beam current exceed
predetermined level, the circuit operates as follows: it increases
horizontal scan rate, and if the excess is still increasing,
a protection scheme dampens CRT on and off the horizontal scan.
This circuit disables the horizontal scanning in cases where there
the following faults:

  1. Too high current in the line of 24 volts.
  2. Excess current of the beam.
  3. Increasing the voltage heater CRT


[ندعوك للتسجيل في المنتدى أو التعريف بنفسك لمعاينة هذه الصورة]
Figure 1 (protection circuit)
WORK PATTERNS


Too high current in the line of 24 volts.

Q589 ON
[ندعوك للتسجيل في المنتدى أو التعريف بنفسك لمعاينة هذه الصورة]

(H-OSC STOP) Apprx. 1V at IC601 Pin
36


Excess current of the beam.

S501 voltage decrease[ندعوك للتسجيل في المنتدى أو التعريف بنفسك لمعاينة هذه الصورة]D581 ON[ندعوك للتسجيل في المنتدى أو التعريف بنفسك لمعاينة هذه الصورة]Q581 ON[ندعوك للتسجيل في المنتدى أو التعريف بنفسك لمعاينة هذه الصورة](H-OSC STOP)
Apprx. 1V at IC601 Pin 36


Increasing the voltage heater CRT.

S590 voltage increase[ندعوك للتسجيل في المنتدى أو التعريف بنفسك لمعاينة هذه الصورة]D590 ON[ندعوك للتسجيل في المنتدى أو التعريف بنفسك لمعاينة هذه الصورة](H-OSC STOP)
Apprx. 1V at IC601 Pin 36
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مُساهمةموضوع: رد: مراجع ودوائر وأعطال و شرح صيانة -CRT-LCD -plasma   الجمعة أبريل 22, 2011 12:22 pm

Power scheme


DESCRIPTION


The chassis MX-5 is used as a power circuit converter emmiternogo inverter
(ESS) of the discrete
type. Power scheme is a scheme of the ESS induction type, which is not synchronized
with the horizontal scan rate (fh).
As in normal operation and in standby power supply circuit ESS is
free-running. It does not use any impulses row
transformer FBT.
The scheme is apuska


Launching shift in this circuit is created by feeding it through a resistor
R803, R804, R805 at the base of the switching transistor Q801. With the help of a diode D803
at the connection point of resistors R804 and R805 fixed voltage, and hence
and the current run. The current launch triggers the transistor Q801. Due to the
clamp diode D803 bias voltage conditions are the same, regardless of
AC input voltage (from 110V to 240V).
Transistor Q801 is locked base current coming from the windings B1 through a resistor
R806 and capacitor C816. At the same time, capacitor C817 is charged shock
with winding B1 through resistor R811.
When the voltage VBE is reached about 0.7 in, the transistor Q802 turns
(ON), and the transistor Q801 is turned off (OFF). When the transistor Q81 is turned off
(OFF), the capacitor C823 is charged current, which flows through diode D817
from the energy stored in the transformer T801. This energy is then accumulated
transformer T801, is output through the diode D817. Transistor Q81 turns
(ON) and maintained in this state by means of induced voltage, which
generated in the winding B1 of the transformer T801.
The scheme is apuskayuschih pulses



  1. At initial power up time management enable (ON) transistor
    Q801 by capacitor C817, which is gradually being charged.
  2. When the transistor Q801 is turned off (OFF) and a capacitor C817, depending
    from the output voltage, negative voltage charge of winding B1.
  3. With increasing charging time of capacitor C817 is extended on time
    (ON) of the transistor Q801.
  4. However, the fluctuations of the voltage winding are significant. Voltage
    winding B1 (VBIP) can be expressed by the following formula:

    Vbip= [Vdc (in)-Vo]
    x[size=25] B
    [/size]1

    The ratio of maximum AC input current to a minimum
    value equal to approximately 8.
  5. Therefore, if the current trigger pulse comes directly from the winding B1, the
    there are significant energy losses. In order to reduce these energy
    loss, is permanently on the current value of the triggering pulse. For
    This part of the scheme included the winding Bs, diode D816 and capacitor S818.
    Voltage winding Bs proportional output voltage (90V). Bandwidth
    Vvz is given by
    the following formula:

    Vb3= Vo x B3=90x[size=25]4T = 8.4V
    [/size]
    Feedback voltage, formed by winding B1 feeds base current to
    transistor Q801 through resistor R816, capacitor C821 and the transistor Q803. When
    transistor Q801 is off (OFF), is the winding Bs produces positive voltage,
    which is fed through a resistor R817 to the base of the transistor Q804, and includes (ON)
    him. Thus, on the transistor Q803 is served locking (OFF) bias. This
    element closes the circuit run.
    Capacitor C820 provides a delay of (ON) of the transistor Q801 by
    change the charging time. A diode D815 is a fast fixing
    diode, which avoids any high voltage
    between the emitter and base of the transistor Q804.

Employment schemes SRF



  1. Scheme SRF controls the maximum turn-on time (ON) of the transistor Q801.
    This is achieved by adjusting the current Ic of the transistor Q801 and thus ensured
    maximum output power.
  2. When the transistor Q801 is on (ON), winding B1 produces positive voltage
    (V BIP), is proportional to the input voltage. When the transistor Q801 is turned off
    (OFF), issued a negative voltage in accordance with an input voltage
    (V BIN).
  3. The relation between VBIP and VBIN can be expressed by the following formula:

    Vbip= [Vdc (in)-Vo]
    x[size=25] B
    [/size]1


    Vbip=- Vo
    x[size=25] B
    [/size]1
  4. When the transistor Q801 is on (ON), the primary winding produces positive
    voltage and capacitor C817 is charged positively. This tension reaches
    value of approximately 0.7 in, enters the base of the transistor Q802, and includes
    (ON) thereof, and therefore disables (OFF) transistor Q801.
  5. When the transistor Q801 is turned off (OFF), the winding B1 occurs negative
    voltage and capacitor C817 is charged negative charge.
  6. If the current charge on the capacitor C817 is no (current feedback diode
    D821), then the maximum on time is determined by the time constant of the chain
    R811 and C817.
  7. With increasing input voltage proportional to the increases and the voltage
    in the winding B1. When the voltage reaches approximately 16V VBIP, the current begins
    proceed along the chain of R810, D805 and D804, and a positive voltage on the capacitor
    C817 increases. Through this on-time (ON) of the transistor Q801 becomes
    shorter and manages the output voltage.

Output management


Stabilization of output voltage + B at 90 are made using
feedback current flowing through the diode D821 and the integrated circuit IC801
to the capacitor C817.
Jobs in standby mode



  1. Switching from normal mode (ON) in standby mode by
    through the transistor Q851.
  2. When the voltage transistor base Q851nahoditsya at a high level, the transistor
    Q850 is turned off (OFF) and the feedback circuitry of standby mode does not work.
  3. When the voltage of the transistor Q851 base is low, the transistor
    Q850 enabled (ON). Starts feedback circuitry of standby mode
    detection scheme up and running standby.

Standby mode control scheme



  1. When the voltage of the transistor Q850 base at a high level, the voltage
    V diode D851 plus voltage VBE of the transistor Q850 provides a flow
    collector current of transistor Q850 through the optocoupler D840.
  2. Capacitor C817 quickly charged through the collector current of transistor
    This photo diode D840. As a result, on-time (ON) of the transistor Q801 becomes
    shorter, thereby regulating the output voltage.
  3. Scheme standby detector uses a 22 channel power. In standby
    mode 22b of the channel decreases to 6.5 at. This can be expressed by
    the following formula:

    V(STD-BY) = [V D 851+ V
    BE Q850] * D852 + R857 = 6.5 B

  4. Resistor R851 is a current limiter for a diode D840. Resistor R850 is
    resistance protection diode D851. In standby mode, through a resistor R850
    current flows 2,7 mA. During standby mode voltage in the channel 90 in the reduced
    to approximately 30V. However, due to leakage inductance of transformer
    T801, this voltage can be below 30V. In order to obtain stable
    feeding conditions at 30V during the standby mode, the circuit adds the equivalent
    resistors R820 and R821.

INDEX OF ABBREVIATIONS AND INSCRIPTIONS USED
In SCHEMES



1H pulses from deflection section .......
pulses from section 1H deflection
1st Field ............................... 1-e field
3-rd Field .............................. Third field
3rd Field ............................... Third field
4 th Field ............................... 4-th field
ACC ...................................... Block avtomaticheskaoy adjust color
AF ...................................... af
AMP ..................................... gain
AMP ..................................... amplifier
ANALOG SWITCH ........................... analog switch
ANT ..................................... antenna
Apprx 1V at IC601 pin 36 ................. approximately 1V on the leg 36 integral
circuit IC601
Audio defeat ............................ suppression of the audio
Audio out ............................... Audio Output
Audio Signal from pin 57 of IC601 ........ audio signal with 1957 feet of the integral
scheme
IC601
Audio Signal goes through Treble filter. audio signal passes through the filter
high notes
Audio ................................... Audio, sound
auto mode ................................ auto mode
auto / manual ............................. manual / automatic
AV out .................................. Output of audio-video
AV TERMINAL .............................. output audio and video
BAND SELECT ............................. range selection
Base Voltage ............................. Voltage base
BELL ref ................................. reference frequency bell-filter
BELL ..................................... bell-shaped filter
BLACK STRECTH ............................ black stretch
BLANKING PULSE .......................... pulse blanking
BOARD .................................... PCB
BPF ..................................... band-pass filter
burst gate .............................. color subcarrier signal pulse
(Momentum iivspyshkil.)
burst processing circuit ................ signal processing circuit i? eaniuoeela
By pass filter ........................... Bypass Filter
Cancel Chroma Blanking .................. prohibition blanking signal tsvetnosti.Capacitance
(PF) .............. capacitance (pF)
Center Frequency Adjustment ............. setting the carrier frequency
change X-tal ............................ replacement of the quartz oscillator
Characteristic of varicap ................ characteristic varicap
CHIP .................................... chip
CHROMA DEcode ............................ decoder chroma
C-IN ..................................... chroma in
circuit ................................. scheme
CLAMP LEVEL ............................. level of fixation
CLAMP PULSE .............................. pulse fixation
CLAMP ................................... fixing scheme
Coil current ............................ coil current
COIL .................................... coil
Collector current ....................... collector current
Collector Voltage ....................... collector voltage
COMPOSITE VIDEO SIGNAL .................. complete television picture signal
CONTROL ................................. Management
CRT HEATER ............................... CRT heater
CRT ..................................... CRT Cathode Ray Tube
DATA SLICER ............................. quantizer data
DC VOL ................................... circuit DC voltage
DECODER ................................. decoder
DE-EMPHASIS .............................. predistortion correction
defeat .................................. quenching, cancellation
DEFLECTION COIL .......................... deflection coil
Delay Adjust Voltage .................... voltage settings of the delay line
Delay ................................... delay line
Demodulation Carrier Amplifier .......... demodulated signal amplifier
Carrier
Frequency
demodulation sound signal ............... demodulated audio
DL time sw ............................... switch delay
DRIVE TRANS .............................. transformer drive circuit
DRIVE ................................... trigger pulse
Dumper Current ........................... Discharge current
DY ....................................... deflection coil
EAR PHONE ............................... Phone
End of identification .................... the end of the identification
Ext AFT amp .............................. external amplifier fine tuning
Frequency
EXT Video IN ............................ External Video Input
f REF ................................... reference frequency.
FILTER .................................. Filter
Finer Adjustment ......................... Fine tuning
First amplifier control range ............ The range of control of the first amplifier
FLYBACK PULSE ........................... flyback pulse
FM DET. ................................ detection of frequency modulation
FM direct out ........................... direct access to frequency modulation
FOCUS ................................... focus
Forward bias ............................. forward displacement
FREQUENCY ............................... frequency
from deflection section .................. (Deviation from section)
From power circuit ...................... with the power scheme
FRONT AV ................................ Contact audio / video on the front panel
gain .................................... gain
GATE PULSE .............................. gating pulse
H OUT TRANS .............................. horizontal output transformer
sweep
HEAT Sink ............................... heat sink
HPE ..................................... High Pass Filter
I / F ..................................... intermediate frequency
IC ...................................... IC
IDENT ................................... ID
IDENTIFICATION .......................... identification
IF AGC Voltage .......................... voltage circuits with automatic
gain control intermediate frequency
IF input ................................ input of intermediate frequency

IIC Buc Control for crystar
(4,43 / 3,58) and System
(NTSC / PAL / SECAM) Selection .............. Management through the bus IIC for quartz
generators (4.43 / 3.58) and the choice of the system (NTSC / PAL / SECAM)

INPUT ................................... login
Input Lock Detector ..................... input sync detector
INTERFACE ................................ Interface
Internal bus ............................ internal bus
IRE ..................................... unit of brightness
LED BRACKET ............................. body diode
LED ..................................... LED
Limiter amplifier ....................... amplifier-limiter
Limiter input (inter-carrier )............ input limiter (internal
carrier)
Local OSC ............................... local oscillator
low pass filter .......................... Low Pass Filter
LPF ..................................... low pass filter.
manual mode ............................. Manual
MIXER .................................... Mixer
MTR ...................................... recorder
Mute Pulse when Power OFF ............... pulse jamming sound off
nutrition
n +1 Field .............................. field n +1
n +2 Field .............................. field n +2
NG ...................................... No
OK ....................................... YES
OPERATION BUTTON ........................ Working buttons
or ....................................... or
OSC ...................................... generator
Oscillation frequency ................... oscillation frequency
OSD ...................................... display on the TV screen
OUT ..................................... output
OUTPUT. ................................ output
Output from Lock Detector ............... output signal sync detector
OUTPUT STAGE ............................ output stage
OUTPUT VOLTAGE ........................... output voltage
picture quality circuit ................. scheme of image quality
PIN ...................................... leg
PLL ref ................................. reference frequency circuits RLL
PLL ...................................... automatic phase control
POWER BUTTON ............................. Power button
POWER CORD .............................. cord
Power OFF ............................... Power Off
Power ON ................................. Power on
POWER SWITCH ............................ power switch
p-p ..................................... in full swing
Pre Ground ............................... pre-ground

Pre-amplified audio signal
amplifies to drive either the speaker
or the head-phone ....................... Pre-amp audio
amplified in order to initiate the work of the speaker or headphones
Phones

PUMP UP ................................. swapping
R / CON ................................... remote control
REF FILTER ............................... reference filter
REG ..................................... regulation
REG ...................................... regulator
Regulator. ............................. regulyator.REM RECEIVER .................................
signal receiver remote control
RESET .................................... reset
Reverse bias voltage ..................... reverse bias
RF. .................................... high (radio) frequency
RF AGC to tuner ......................... with automatic adjustment scheme
amplification of intermediate frequency on the tuner
RF-AMP .................................. high-frequency amplifier
R-Y ...................................... chroma signal R-Y
SAW filter .............................. SAW filter, the filter surface
acoustic waves
SCL ..................................... channel serial clock
SCREEN ................................... screen
SDA ..................................... channel serial data
SECAM Identification 1 ................... SECAM identification of a
SECAM identification II ................. Identification SECAM II
SECAM .................................... SECAM
Second amplifier control range ........... The range of control second amplifier
Set ..................................... job
SIF SELECT ............................... choice of intermediate frequency audio
STAND BY ................................ Standby mode
Stand-by 12 V High DET. ................. detector exceed 12 duty
regime
Start ................................... Home
STOP .................................... stop
Switching. ............................. switching
synthesizer phase control ............... phase control of the synthesizer
System change ............................ Replacement of

System is changed to SECAM
X-tal is changed to 4,43 ................ system is replaced by quartz SECAM
generator is replaced by 4.43

TELETEXT CIRCUIT ......................... Teletext circuit
TELETEXT ................................ teletext
THERMAL PROTECTION ....................... temperature protection
Tint ..................................... shade
to chroma section ....................... (Per section chroma)
to interface section .................... the section interface
Tone .................................... tonality
TRANSMITTER ............................. transmitter
TRAP .................................... Notch Filter
Treble Control 0-5V from MPU ............. control signal is high tones
0-5c
comes from the microprocessor MPU
Treble filter ........................... filter of high tones.
TREBLE .................................. high tone
TUNING .................................. Customize
TV IN .................................... input television signal
unlock .................................. not synchronized
Update system in IIC bus status data ..... Update the information state
IIC bus
Video out ............................... video output
VIDEO TONE .............................. color video
Video ................................... video
voltage decrease ........................ reduction of stress
voltage increase ........................ increase the voltage
Voltage .................................. Voltage
Volume Control 0-5V from MPU ............ signal volume control 0-5V
from the microprocessor MPU
Volume ................................... volume
V-PULSE MODE ............................ mode of impulse voltage
V-RAMP MODE .............................. sawtooth mode
V-RAMPBACK .............................. Feedback on the sawtooth
Weak signal ............................. weak signal

When Power Off Mute Pulse activates
the Q1130 to stop the input signal
to the amplifier ........................ power outages pulse jamming
activates the transistor Q1130 to stop the supply of input
Amplifier

X-RAY ................................... X-radiation
X-tal 3,58 / 4,43 identification ........... definition of the type quartz oscillator
3,58 / 4,43
X-TAL .................................... crystal oscillator
Y BOARD .................................. charges Y
Y SW Out ................................. Output switch signal Y (luminance)
Y-IN ..................................... input signal brightness
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مُساهمةموضوع: رد: مراجع ودوائر وأعطال و شرح صيانة -CRT-LCD -plasma   الجمعة أبريل 22, 2011 1:35 pm

Colour TV FALCON 54TTS6155 (Chassis A-2000)
Repair manual



Main technical characteristics


ChassisA-2000
Kinescope21''A51KQN011X
High Voltage27.5 kV
Automatic selection ofPAL / SECAM - B / G, D / K,
(Video - NTSC -3,58 / 4,43)
Supply voltage170 ... 250 V 50/60 Hz
ConsumptionStandby: 5 W or less
Operation: no more than 80 W
Rated power output channel audio3 W
Speaker3 Watt 16 ohm
Antenna Impedance75 Ohm
TunerPLL tuner DT5-BF14D
Accepted Feeds:
CFChannels 1-5, 6.12 standard D / K;
Channels 2-4, 5.12 standard B / G
DMVChannels 21-60 standard D / K;
Channels 21-69 Standard B / G
CATVchannels TC1-SK18 standard D / K;
channels S1-S20 Standard B / G
Intermediate frequency:
Video38.9 MHz
sound32.4 MHz (D / K)
33.4 MHz (B / G)
chroma34.47 MHz (PAL)
34.5 MHz (SECAM)
34.65 MHz (SECAM)
35.32 MHz (NTSC)
Number of Programs60
Connecting external devicesBuilt-in EURO-SCART
Connector RCA (AUDIO-VIDEO, IN / OUT)
Teletext8 pages
Dimensions (width x height x depth):512 x 460 x 475 mm
Net weightNo more than 24 kg
AccessoriesRemote Control
(2 batteries type AA)
Operating Instructions

Specifications subject to change without notice.
A-2000 chassis. Brief description of circuits included in the chassis.



List of chips:
SDA555XFL/A-2000Control processor
TDA8842/N2Single-chip video processor
TDA8356Vertical
TDA6107Three-channel video amplifier
TDA7056Low-frequency amplifier 3W
STR-S5707Hybrid chip power supply
KA7630Stabilizer of the secondary power source

A-2000 chassis is designed with a set of modern integrated and hybrid
circuits of the world leaders in the design and manufacture of chips as
"PHILIPS Semiconductors", "INFINEON Technologies" (branch "SIEMENS"),
"SANKEN".
Microcontroller controls SDA555XFL/A-2000 - one of the latest
developments "INFINEON Technologies" with built-in teletext decoder (10
pages) and a powerful generator of OSM on board, TVText Pro. In piping
processor uses a minimal number of external add-on components. Brief
characteristics of the processor:
Hardware



  • 8-bit embedded microcontroller (8051 compatibility);
  • More than 128 KB of internal ROM;
  • More than 1 MB external ROM / RAM;
  • More than 16 KB of internal XRAM;
  • Simple external 6 MHz quartz for all domestic fixed systems;
    Simultaneous production of TTX, VPS / PDC, and WSS (16:9);
  • The new digital limiter with automatic
    detection and alignment of high-quality distortion VBI-ling. detection
    even in low signal;
  • 0.25 ѓm CMOS technology and 2.5/3.3V;
  • Two 16-bit timer, one-hour preservation, and one - the timer control IR;
  • PWM part (two channel 14 Bit, 6-channel 8 Bit);
  • ADC (4 channels 8 Bit);
  • UART interface;
  • Unified character of the settings for all based on западно-/восточно-европейских and Arab / Persian languages;
  • Programmable screen size (25 rows x 33 ... 64 columns);
  • Flexible matrix (12x9. .. 16 pixels);
  • CLUT with more than 64 of 4096 flowers;
  • Smooth scrolling cursor (pixel by pixel)
  • Tested around the world Firmware-ins for data acquisition and IR-detection;
  • Advanced Editor Display (TEDIPRO) for quick and easy OSM-and improve the font;
  • Support for various emulators (Hitex, Kleinhenz);

TDA8842/N2 video processor developed in the late 90's for television the
concept of GTV-1000. This single-chip video processor with advanced
technology bus I2C. Below are brief specifications Products:

  • IF demodulator circuit with no external PLL circuit;
  • Easily adjustable many standard FM sound demodulator (from 4.5MGts to 6.5MGts);
  • Audio switch;
  • Flexible source selection with CVBS switch and Y (CVBS) / C input;
  • SECAM decoder integrated circuit;
  • Integrated delay line luminance signal;
  • Function Black stretch;
  • Function Blue stretch;
  • The scheme of auto white balance by two points (in black and white);
  • Linear RGB input and fast blanking;
  • Function "blue back" in the absence of a signal;
  • Management of various functions by bus;
  • Power consumption 850mW;
  • High quality signal processing system, SECAM.

As the applied field sweep pavement IC TDA8356. Brief characteristics of the circuit:

  • Overtemperature protection;
  • Protection against short circuit of output pins to each other;
  • Protection against short circuit of output pins to ground or power supply;
  • The minimum number of external components.
    Pavement chip with a symmetrical input connected to a video processor
    TDA8842/N2 with a minimum number of elements and allows the maximum
    efficiency control the parameters of the raster.

Video amplifier is made on a chip TDA6107Q. This three-channel video
amplifier output, made by high-voltage DMOS technology with fixed gain,
and requires for its work the minimum number of external components.
Inputs R, G, B chips are connected directly to the video processor
TDA8842/N2 without any additional amplification. Brief characteristics
of the circuit:

  • Bandwidth of 4.0 MHz video signal;
  • Fixed gain of 50;
  • Slew rate signal 900 V / s;
  • One power supply;
  • Overtemperature protection;
  • Measurement scheme for autobalance.

As a low-frequency amplifier used chip TDA7056. This bridge VLF power 3 Watts. Brief characteristics of the circuit:

  • Output power at load 16 ohms 3 watts;
  • Output protection against short circuit on the ground or power supply;
  • Protection of all the findings from the breakdown by static electricity.

Power supply chassis is made on a hybrid chip STR-S5707 with a
built-power transistors manufactured by "SANKEN" (Japan). Brief
characteristics of the circuit:

  • Case isolated small-sized type of SIP;
  • Protection against breakdown;
  • Overtemperature protection;
  • Low consumption of power in standby mode;
  • Ease of connection scheme and a minimum of
    external components connected to the chip. Using this chip allowed us to
    obtain a power supply with high efficiency, minimal losses and low
    consumption of television in standby mode.

Voltage regulator +5 V and +8 V-chip is made on the KA7630. Brief characteristics of the circuit:

  • Overtemperature protection;
  • Output protection against short circuit on the ground or power supply;
  • Log DISABLE relief +8 V when you turn on TV in standby mode;
  • Output RESET to reset the microcontroller;
  • Small internal loss. IC KA7630 stabilizer
    used for +5 V / +8 V to provide power to all parts of the low-voltage
    circuits, including tuner, micro-management and video processor as a
    stand-by and running.

Application of this chip set has allowed the chassis design with an
optimal price-quality ratio. TV's chassis A-2000 into technology to
produce, convenient in maintenance and operation, have the opportunity
to build additional functionality (teletext, games, etc.).
Description of the principal electric circuit TV "FALCON 54TTS6155 (chassis A-2000).



The main components included in the chassis:
SDA555XFL/A-2000Microcontroller control
TDA8842/N2Single-chip video processor
24LC08B / PEEPROM memory
TDA8356Vertical
TDA6107Three-channel video amplifier
TDA7056Low-frequency amplifier 3W
STR-S5707Hybrid chip power supply
KA7630Stabilizer of the secondary power source
LM317LZStabilizer of the secondary power source
SFH 5110-36Integral IR receiver
DT5-BF14DPLL-Tuner
TSM-3934A1Pulsed power transformer
FSA36012MTDKS
Management system


The control system is based on a microcontroller and nonvolatile
electrically SDA555XFL/A-2000 - clears the memory (EEPROM) 24LC08B / P,
IR receiver SFH 5110-36, remote control and button control panel.
IC SDA555XFL/A-2000 a single-chip 8-bit microcontroller with 128 KB of
internal ROM, 16 KB of internal XRAM, two 16-bit timer, one-hour
preservation, and one - the timer control IR, shaper signal OSD and FB
("fast Blanking "for the OSD menu).
Log RESET (vyv.33) is required to "launch" of the microcontroller at power. This signal produces a voltage KA7630.
EEPROM stores the configuration with 60 channels, the picture settings for all programs and the values ​​of the volume.
Command from the remote control via infrared rays taken an integral IR
receiver SFH 5110-36, converted to a pulse signal and transmitted to the
microcontroller, which is decoded and executed. To connect the keyboard
control pin is used. 1918 microcontroller. Determining which button is
pressed at the moment, going through the analog - digital conversion of
input voltage, defined by the voltage divider resistors R102 - SB 107
and buttons 101 - 107.
To control the standby mode uses pin. 3 STBY microcontroller. Supply
voltage 2.5 V with this conclusion on vyv.4 stabilizer KA7630 leads to
release tension +8 powering the video processor. From the same pin. 3 of
the microcontroller is managed optocouplers D202 RS817 (via transistors
VT103, VT104), which carries a chip switching power supply in batch
mode to reduce power consumption power supply.
The microcontroller generates OSD menu and blanking signal. R, G, B
components of the OSD menu are served on vyv.23, 24, 25 GPU. To
synchronize the OSD menus are lower impulses H SYNC (vyv. 1919
microcontroller) and the human impulses V SYNC (vyv. 1920
microcontroller).
To synchronize all the internal circuitry of the microcontroller used
quartz ZQ101 6 MHz (vyv. 34 and 35 of the microcontroller).
Signal processing circuit


PLL - Tuner DT5-BF14D produce selection and amplification of input
signal range for CF, UHF, CATV, and conversion to intermediate
frequency.
Office of the tuner (tuning to channels, range switching, switching
between programs) by the microcontroller SDA555XFL/A-2000 bus I2C.
The output of the tuner IF signal fed to a preamplifier, made on the
transistor (VT301), and after the filter SAW (surface acoustic wave)
ZQ305 K2955M. SAW filter selects the desired frequency band of the
spectrum of the output signal of the tuner. Since the SAW filter formed
by the drive signal to the input drive VPU TDA8842/N2 (vyv. 48 and 49).
TDA8842/N2 in the video is converted IF signal (38.9 MHz) PLL
demodulator and receive a full color video (vyv.6 VPU). Parameters of
the PLL demodulator define the elements of R335, S366, S325 vyv.5
connected to the VPU. Video processor, depending on the level of the
input IF signal coming from the tuner produces a signal AGC (vyv.54 TUN
AGC OUT). APCHG tuner is carried on the bus I2C. The signal across the
emitter-follower (VT304), a notch filter L303, ZQ303, ZQ304, through the
emitter follower (VT305) goes to the video processor (INT CVBS IN
vyv.13). Inside the video processor is processing the video signal
matrixing and receiving output R, G, B signals (vyv.19, 20, 21). The
video processor allows the system to decode PAL, SECAM, NTSC 3,58, NTSC
4,43. Inside the video processor is a circuit identification system
colors. For normal operation, decoding scheme, and color recognition
systems require the standard three-level synchronization pulse on SSC
vyv.41 video processor.
With the emitter follower (VT304) removed the sound IF signal that
enters the circuit bandpass filter: S326, S322, L302, VT303, ZQ301,
ZQ302. After filtration, the sound IF signal to the input of SIF IN
(vyv.1) video processor. In the video processor is FM demodulation IF
sound signal, its amplification (gain adjustable). The amplified audio
signal is fed to the pin. 15 AUDIO OUT video processor for subsequent
submission to the low-frequency amplifier or a SCART or RCA connectors.
Power of low frequency (VLF) is made on the bridge chip TDA7056 (maximum
output power 3 W). Control volume by varying the amplitude of the input
signal to vyv.3 VLF. Changing the amplitude of the signal is carried
out in the video processor and is controlled by a microcontroller on the
bus I2C. Mode Mute (MUTE) is carried out in two stages: first stage -
the filing with the microcontroller signal high level (2.5 V) at the
base of the transistor VT302, the second phase - reduction of the
amplitude of the output video processor to zero.
Formed by R, G, B signals from vyv.19, 20, 21 on three-channel video
processor receives an integral video amplifier TDA6107. TDA6107 chip
amplifies the input R, G, B signals to levels required to operate CRT.
Video amplifier has the following properties: a fixed gain of 50, the
signal slew rate 900 V / s, single-voltage, overtemperature protection,
measurement scheme autobalance, video bandwidth 4.0 MHz.
The TV used auto white balance circuit at two points: in black and
white. Auto white balance on two points made in this way: one half-frame
by measuring generation of an pulse to determine the current-rays in
black, while the other half-frame in white.
The scheme of auto white balance works as follows: video processor
generates a metering pulses (19, 20, 21 line video) in the R, G, B
signals, and video amplifier has a measuring circuit auto white balance,
and this circuit produces responses measuring pulses corresponding to
the current of each beam kinescope at levels which video processor
changes the ratio of R, G, B signals to maintain white balance. Below
are brief specifications VPU:

  • IF demodulator circuit with no external PLL circuit;
  • easily adjustable multi-standard FM sound demodulator (from 4.5 MHz to 6.5 MHz);
  • audio switch;
  • Flexible source selection with CVBS switch and Y (CVBS) / C input;
  • SECAM decoder integrated circuit;
  • Integrated delay line luminance signal;
  • function Black stretch;
  • function Blue stretch;
  • scheme auto white balance by two points (in black and white);
  • linear RGB input and fast blanking;
  • function "blue back" in the absence of a signal;
  • control various functions via bus;
  • power consumption of 850 MW;
  • high quality signal processing system SECAM.
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مُساهمةموضوع: رد: مراجع ودوائر وأعطال و شرح صيانة -CRT-LCD -plasma   الجمعة أبريل 22, 2011 1:36 pm

Chain developments


Vertical.


Vertical output stage is made on the bridge chip TDA8356. It has in its
composition: thermal protection, protection against short-circuit output
terminal circuits, fault protection output pins to ground or power
supply. To work chip requires two power supply 45 V (vyv.6) and +13
(vyv. 3) chip.
As a master oscillator sawtooth voltage is used the video processor
TDA8842/N2. Sawtooth voltage is removed from vyv.46 and 47 video
processor and passes through the RC circuit (R407, C406, R408, C408) to
the input circuits Vertical.
IC TDA8356 generates momentum for vyv.8 protection scheme, which through
the VT402 comes to video processor for vyv.22. The same impulse comes
to a microcontroller and used to synchronize the OSD menu by frame.
Failure of microcircuit TDA8356 pulse is not generated, and the video
processor disables the output R, G, B signals to avoid burn-through
phosphor CRT.
Line scan.


Cascade line scan performed on TDKS FSA36012M, output transistor
2SD1878. Job line scan is based on the principle of energy storage
during flyback by rows. The video processor generates a start pulse line
scan. This impulse is fed to a cascade of driver VT401, which is loaded
on the interstage transformer TV401 TD10A2. Transformer stores energy
in the winding during the open state of the VT401 (transistor called
positive trigger pulse line scan). At the end of the positive pulse the
transistor is closed, there is a pulse of self-induction emf due to the
energy accumulated in the primary winding. This impulse is transformed
into the secondary winding of the transformer and is used to reduce and
then completely turn off the output transistor base current VT403.
Supply voltage 123 B comes from the power source through inductor L402,
the primary winding of TV402 and choke L401 to the collector of the
transistor VT403.
In steady state, the scheme works as follows. In the first half of the
direct magnetic energy stored in row deflection coils during the
previous process deviations, creates a linearly decreasing current
deviation moves the electron beams from the left edge of the screen to
its middle. This current flows through the deflection coil OS coil
linear lines, the condenser forward run S421. Capacitor is recharged
S421 flowing current deviation.
By the time of arrival of rays to the middle of the screen when the
current deviation is reduced to zero, from the transformer to the base
TV401 VT403 comes the positive momentum of its opening. At a time when
the current in the deflection coil is zero, all energy is concentrated
in the row circuit S421. This capacitor discharging through the open
transistor VT403 and lower coil current creates a growing rejection of
the second half of direct stroke that moves the electron beams from the
middle of the screen to his right side.
By the time of arrival of rays to the right edge of the screen closes
transistor VT403 negative voltage pulses, coming in at its base with a
secondary winding TV401. The collector of the transistor VT403 while
there positive sinusoidal voltage pulse as a result of the oscillatory
process occurring in the loop formed by parallel connected coils OS TDKS
primary winding and a capacitor reverse S416. Impulse voltage flyback
in this circuit causes a rapid change in polarity deflection current,
which causes the rapid movement of electron beams from the right edge of
the screen to the left, ie reversal of the beam.
TDKS used as a source of secondary stress. Momentum reversal of the
collector closed VT403 reaches 1100 V (during the return stroke) and
applied to the primary winding TDKS This impulse is transformed into the
secondary winding and is used to create the secondary supply voltages
(supply video amplifier 200 V, power chips Vertical 45 In and 16 V
heater voltage kinescope) and the second high-voltage anode 27 kV, the
focusing voltage and accelerating voltage.
With the pin. 7 TDKS the resistor R425 stands out signal for the circuit
current limiting ray (OTL), which through the transistor VT404 comes to
vyv.22 video processor.
With the resistor R418 across the resistor R417, diodes restrictive
VD408, VD409 and resistor R416 momentum reversal comes to the video
processor (vyv.41 SC) to form a three-level pulse synchronization SSC.
Switching Power Supply


Circuit portion electrically connected to the network AC voltage of 220V.


Power supply AC 220V applied to the connector HR202, and passing through
the fuse FU1 4A, goes to the power switch button SA201. Further, the
mains voltage is filtered S201, L201, C203 and comes to circuit
full-wave rectifier VD202-VD204. Capacity of the S217 is charged to a
voltage of 310 V, which goes to the power of the pulse transformer
winding 4.1 Power (TPI) TV201. The second end of the power winding is
connected to a power switch, integrated in the IC D201 STR-S5707. Pulsed
current flowing into the power coil is 4.5 A, the magnitude of the
voltage 600 V. The pulse repetition rate depends on the load power and
is adjusted automatically (run 20-30 kHz). In addition, to reduce power
consumption during the transition into standby mode (STAND BY) through
optocoupler D202 is converted power source in batch mode: packets of
pulses alternating with pauses, when the power transformer is not
pumped.
Windings 5-7 and 7.6 TPI used to control and the supply voltage to IC
D201. Impulse voltage is removed from the winding 6-7, and then goes to
the rectifier diode is collected on VD207, S206 and capacitor to the
input voltage IC pin. 9. The value of the supply voltage is 15 V. For
the initial launch of IC (power supply) is a resistor R206. Winding 7.5
TPI is used to control the opening and closing of integrated on-chip
power switch D201. Control pulses are removed from vyv.8 IC D201 and a
resistor R202, capacitor C202 is served at the base of the integrated
power key.
Alternating current up to 3,5 A, serving to degauss CRT, flows only when
turning on the TV, and then after heating posistor R201 T170 is
limited.
Part of the circuit is not electrically connected to the network AC voltage of 220V.


With the secondary windings of pulse transformer off the voltage supply
for the cascade of line scan 123 V power amplifier low frequency of 16 V
and +15 V for the voltage regulator on the D206 IC KA7630. Voltage
regulator D206 provides two fixed values ​​of +5 V, +8 V. +8 V voltage
is turned off by the incoming signal from the microprocessor to the
DISABLE pin. 4 D206. This ensures the reduction of energy consumption in
standby mode. For distribution to low power supply voltage used by
consumers to the regulated voltage D203, D204, D205 performed on
LM317LZ. To reduce the parasitic influence of the cascades at each other
for power circuits in each circuit is low-pass filter: the inductance
of 10 uH, 10 uF electrolytic capacitor.
Troubleshooting TV FALCON 54TTS6155.


1. TV does not turn on, standby LED is not lit.
Possible causes: Loss of power cable, insert a fuse blown FU1, defective
power switch SA201, the failure of circuits switching power supply
STRS5707, pulse transformer, etc.
Methods of finding fault:
check the integrity of the insert fuse FU1. Possible cause of burnout
became FU1 breakdown diodes VD203-205, capacitors S201, S203, S208,
S209, S213, S214, S217, a power transistor chip STR-S5707. Break power
transistor can be determined by measuring the resistance between
terminals 1 and 2 pre vypayannoy chip. In a faulty chip device will show
the presence of a short circuit between pin. 1 and 2. Print a chip
failure can break the capacitor C204. In a working scheme in operation
(standby) mode rectifier switching power supply should be removed
following voltage: 123 V (145 V), +15 V (+16) +16 (+17 V).
Another group of failures is the lack of power linear regulators for
KA7630 vyv.1 and 2. Check the flow of voltage pin. 1 and 2, KA7630 and
+5 V on vyv.9, both in working and in standby mode the TV. Just control
the voltage at vyv.4 KA7630. In a working circuit in standby mode, it
should be about 0 V, and in operation around 2.5 V.
Malfunction of linear stabilizers D203, D204 LM317LZ, feeding
microcontroller SDA555XFL. The absence of any supply voltage of the
microcontroller: +3,3 V; +3,3 VD; +2,5 V; +2,5 VADC; +2,5 VDAC.
2. TV is not included with either the remote control (remote
control), or when you press the control board, LED lights and standby
mode does not blink when you press the remote control or buttons on the
control board.

Possible reasons: failure of the remote control, IR receiver failure,
lack of food on the findings of the microcontroller SDA555XFL (fault
line stabilizers D203, D204 LM317LZ), malfunction of the
microcontroller.
Methods of finding fault:
Check for all voltages of the microcontroller: +3,3 V; +3,3 VD; +2,5 V;
+2,5 VADC; +2,5 VDAC. With proper operation of all sources of supply of
the microcontroller and the availability of all the supply voltages on
its findings to check the flow with pin. 3 on the microcontroller pin. 4
"DISABLE" linear stabilizer KA7630 voltage 2.5 V at the TV to the
operating mode of the panel. In a normally functioning scheme of feeding
2.5 B on pin. 4 linear regulators KA7630 causes stress on the +8 V pin.
8, feed the video processor TDA8842. 2.5 In the absence of voltage on
the pin. 3 microcontroller with the TV on in the operating mode of the
duty a malfunction of the microcontroller. If the voltage goes to 2.5 in
the pin. 4 linear regulators, but the +8 V does not appear, then the
faulty linear regulator KA7630.
3. TV does not turn on the LED standby light flashes on their own
without giving the command, or when you press the remote control and
buttons on the control board.

Possible reasons include: LED standby light flashes on their own about 1
per second, this means that the chip EEPROM is not responsible for the
microcontroller I2C bus. LED standby light flashes independently about 1
every 3 seconds, it means that the video processor TDA8842 is not
responsible for the microcontroller I2C bus.
Standby LED flashes when a signal from the remote control or by pressing buttons on the control board.
Methods of finding fault:
In the case of EEPROM check the supply voltage +5 V-uC on vyv.8 D102
24LC08B / P. If this voltage does not, check the chain of supply.
In the case of the video processor check the flow of voltage to +8 V
pin. 12 and 37 of the VPU. +8 V voltage must be supplied with the video
processor on the only working TV mode (the presence of 2.5 B on pin. 4
KA7630 see above).
Just check the level converter bus I2C FET VT105 and VT106. With all the healthy elements should be replaced by chip EEPROM.
Press any button on the control board and check whether the command
passes to the microcontroller (standby LED will flash when the button is
pressed). If a team has passed, so faulty remote or IR receiver. Check
the supply voltage +5 V and the output signal from the infrared receiver
SFH 5110-36 when submitting commands from the remote control. If a team
passes, but TV is not included in the operating mode, check the +8 V
supply GPU. If the command fails, check the remote control and IR
receiver (with no command signal output of IR receiver "pull" to + 5 V).
4. No picture on the TV screen.
Possible causes: the lack of a high voltage CRT anode on the second, no filament kinescope.
Methods of finding fault:
if there is sound, but no screen, check for high voltage and filament in
the CRT. The absence of stress a malfunction of the cascade line scan.
Check the entry 123 in the collector output transistor of the cascade
line scan VT403. If the voltage is 123 In the absence, check the source
of this tension: diodes VD211, inductors L401, L402, capacitors S233,
S417. Cause of failure of the throttle L401 or L402 may be the breakdown
of the transistor VT403.
In the presence of voltage on the collector 123 in VT403 check the flow
of start pulse line scan at the base of the transistor. In the case when
the momentum start there, replace the transistor VT403 on a known
working. If this does not work, then went down TDKS.
In the absence of trigger pulse line scan check sequence circuit arrival
of these pulses from the video processor TDA8842 vyv.40 to the base of
the transistor VT403. The reason for the absence of pulses at the base
of the transistor VT403 may be the fault of: interstage transformer
TV401, a transistor driver VT401, no power supply +15 V stage driver
(VT401), S401, VD401, of the GPU, etc.
In the case when high voltage is, and there is no filament (filament
picture tube not lit), check the integrity of the filament kinescope
(vyv.9 and 10 in the basement of a kinescope) and resistor R505.
Attention! Rated heater voltage kinescope A51KQN011X is 6.1 in
the effective voltage. The reason for the lack of high voltage and
filament may be a violation of connection pins TDKS.
5. No picture, screen is.
Possible causes: the lack of R, G, B signals on the findings of a
kinescope, the video amplifier fault TDA6107Q, the absence of voltage
video amplifier, tuner, radio circuit, a faulty video processor, etc.
Methods of finding fault:
check that the R, G, B signals at the input of video amplifier TDA6107Q.
In the presence of R, G, B signals and the nominal supply voltage
circuit 200 to replace the chip video amplifier with a known good. In
the case of R, G, B signals are not available, check their availability
on vyv.19, 20, 21 GPU. In the absence of R, G, B signals on these
findings Check the circuit autobalance (measuring the presence of pulses
on lines 19, 20, 21 R, G, B signals and response pulses generated video
amplifier TDA6107Q). If no pulse video amplifier TDA6107Q, a video
processor to form, the defective chip video amplifier. In the case where
the video processor TDA8842 does not generate a pulse measuring
autobalance, faulty video processor itself, respectively.
In the case when the screen picture tube glows white and visible line
flyback, with the TV itself can switch to standby mode (activated
current protection ray picture tube), check in at 200 vyv.6 chip video
amplifier TDA6107Q. In the absence of this voltage Check the source,
which forms this tension: VD405, C413, C423, R504, C501, C502 and video
amplifier. When you turn on the TV operation mode is strong overheating
and darkening of the resistor R504, then we can say that vyv.6 (input
200 V) Video Amplifier knocked to the ground.
Check the pulse on the pin protection. Vertical chip. In its absence,
the video processor turns off the output R, G, B signals. Possible cause
- the failure of circuits Vertical.
If the TV screen illuminates the "snow" is likely to be defective or not
working tuner setup for channels. Serve on vyv.8 tuner IF signal
frequency of 38.9 MHz. When you see pictures, check power tuner +5
V-TUN, voltage 45 V and serviceability zener KA33V, forming the voltage
used for tuning the tuner to the channel. On failure tuner says flashing
LED standby about 1 every 5 seconds, it means that the tuner is not
responsible for the microcontroller I2C bus.
Check if the drive is signaling frequency 38.9 MHz in the presence of
vyv.6 GPU video. In the absence of video replace the SAW filter on
known-good if it did not help, then we can conclude that the defective
video processor itself. In the case where the signal to vyv.6 video
processor is, and image on the screen do not consistently check the
chain of transmission of video signal with up to vyv.6 vyv.13 VPU:
VT304, VT305, ZQ303, ZQ304, C306, etc.
6. No picture, sound on AV input (SCART, RCA).
Possible causes: a video - a fault circuit video feed to vyv.17 VPU
(R346, R347, C340) or malfunction of the video processor (internal
switch external / internal signal), and sound - the fault circuitry, the
sound component of the AV signal (R318, R320, R322, S318, R328, C320)
or malfunction of the video processor.
Methods of finding fault:
supplied via a SCART or RCA video, turn the TV to Video mode. Check the
circuit proceeds to vyv.17 video video processor. If the signal at the
pin. 1917 GPU is a picture there, it is faulty video processor itself.
Similarly, check the chain received a sound component of the chain of
R318, R320, R322, S318, R328, C320 to vyv.2 video processor. When sound
is present on vyv.2, but no sound, check out low-frequency amplifier
(see below). After this we can conclude performance video processor.
7. No sound or sound is distorted.
Possible causes: faulty low-frequency amplifier TDA7056, food chain of
the VLF (+16 V), the control circuit of the mute (MUTE), video
processor.
Methods of finding fault:
if there is no sound or it is corrupted by a signal on the RF-input of
the tuner, and when a signal is applied to AV input sound is normal,
check the accuracy of the settings on the channel, VT303, bandpass
filters ZQ301, ZQ302 and other elements involved in the IF bandpass
filtering of sound ( SIF).
In the absence of sound (if a signal is applied, both in RF, and AV -
input) to monitor the presence of a signal at the pin. 15 video
processor. If the signal on vyv.15 there should be verifiable by the
low-frequency amplifier, enrolling him in 16 (2 vyv. ULF) and the
serviceability of the control circuit shutdown signal (VT302, a
microcontroller). Mute (mode MUTE) is energizing the base in 2.5 VT302
and decrease the signal to zero at the pin. 15 video processor. Volume
control is on the I2C bus. If the signal on the pin. 15 video processor
is, and at vyv.4 microcontroller voltage 2.5 V (no inscription on the
screen "mute"), then the microcontroller is faulty. In the case when all
signals arrive at the video processor circuit mute and low-frequency
amplifier operable, it is likely to fail out the video processor.
In situations where the distortion depends on the standard signal (B /
G, D / K), should be checked items ZQ301, ZQ302, R326, R327, ZQ305.
8. No Vertical.
Possible causes: defective chips Vertical TDA8356, no power +16, +45 V, no input sawtooth pulse field sweep.
Methods of finding fault:
Check the power supply circuits for Vertical TDA8356 vyv.3 about +13 V
(+16 to resistor R411) and vyv.6 45 V. In the absence of any stress test
sources, forming these strains (R419, VD406, C414 for 45 B and R420,
VD407, C415, C407, R411 to +13).
In the case of the two voltages on pins Vertical verify receipt of the
input sawtooth pulse field sweep at the pin. 1 and 2 of TDA8356 with the
video processor (vyv. 46 and 47). If the pulses are received, and the
field sweep is not likely to be defective chip field sweep. In the case
where the pulses have to pin .46 and 47 GPU, and the pin. 1 and 2
TDA8356 not, you should check the chain of supply of these pulses. If
the pulses are absent on the pin. 46 and 47 of the video processor, you
probably worn out the video processor.
Designation of the buttons on the remote control



[ندعوك للتسجيل في المنتدى أو التعريف بنفسك لمعاينة هذه الصورة]
1 POWERTranslated from the TV in standby mode and back to work
2 0.........9Direct selection of programs
3 TIMEConclusion of the current time
4 CH.Switching programs around the ring in the direction of increasing numbers of channels
5 CH.Switching programs around the ring in the direction of decreasing numbers of channels
6 VOL.Increasing Volume
7. VOLDecrease volume
8 Q. VIEWCalling the previous program
9 -/--The choice of one / two-digit program numbers
10Go to the game, "QUIZ"
11 FUZZYThe choice of picture settings
1912 DISPDisplays the program number and the hours
13 MENUCalling the menu
14 TV / AVTranslation of the TV to video mode and back
15 MUTESwitch on / off sound
16 TV / incCalling the Teletext (Button TV / inc only works for versions of the TV with teletext)
The remaining buttons are shown in the figure are used only when the
remote control in service mode and are referred to hereinafter
SERVICE MODE


To go to the service menu sequence, press DISP, EXPAND, TIME on the
remote. Appears on the TV table: The number after the inscription
SERVICE means the version number for the processor (SDA555XFL).

[ندعوك للتسجيل في المنتدى أو التعريف بنفسك لمعاينة هذه الصورة]
The number after the inscription TIME indicates the number of hours,
worked out the TV from the time of commissioning. Time parameter is read
from memory EEPROM.
The transition from one section to another by pressing the appropriate buttons on the remote CH.
The same button, you can move from row to row in each section.
Adjustment within the string section conducted using the appropriate buttons on the remote VOL.
Output from the string section is the MENU button on the remote. This same button exits the service mode.
PRESET



[ندعوك للتسجيل في المنتدى أو التعريف بنفسك لمعاينة هذه الصورة]
In the PRESET regulated two parameters AGC and IF-PLL.
Setting the threshold of the AGC is concerned VOL button on the remote
control when a signal is applied to radiovhodu with an amplitude of 1.41
mV (63 dB / uV). The voltage threshold for the AGC as the file AGC =.
In line IF-PLL is set intermediate frequency-Video and schemes APCHG
38.9 MHz. When adjusting the IF-PLL can change the figure on line APCHG.
This figure shows the state of the circuit output APCHG, which is
normal, if APCHG = 2 or 3.
AGC parameter can be set automatically using the red button remote
control. For this purpose, radiovhod previously served a normalized
signal with an amplitude of 1.41 mV (63 dB / uV) and made adjustment to
the signal.
WHITE BALANCE



[ندعوك للتسجيل في المنتدى أو التعريف بنفسك لمعاينة هذه الصورة]
The procedure of white balance should be carried out in a darkened room,
ie, TV screen should not be subjected to illumination from external
sources. Operations are carried out as follows.
1. TV warm up for at least 15 minutes. running.
2. Installs the accelerating voltage. To do this go into the line and
set the VSD VSD = 1, the display shows a thin horizontal stripe.
Regulator accelerating at TDKS (SCREEN) to ensure that the glow of the
band was barely noticeable. Set value of the accelerating voltage
provides the correct operation of the circuit autobalance.
3. In the transition to the rows of C LEV and S BRT set values ​​subkontrastnosti and subyarkosti respectively.
4. White balance is adjusted with the drivers of red, green and blue (R
DRV, G DRV, B DRV). Norma white level x = 0,3; y = 0,31. Installation is
the corresponding buttons on the remote VOL.
GEOMETRY



[ندعوك للتسجيل في المنتدى أو التعريف بنفسك لمعاينة هذه الصورة]
In line SBL establish the linearity of the field sweep quenching the
lower half of the screen and the achievement of the symmetry of the
upper and lower parts of the screen. To this end, in line with the value
V SLOPE SBL = 1 is done changing the slope, "saws."
Upon reaching the linearity of the field sweep the upper limit of the
lower (quenched) half of the screen must coincide with the center of the
blue central cross.
Lines V SHIFT, V AMP, S CORR, H SHIFT produced respectively in the
vertical movement, setting the image size on the frame, S-correction
frame saws, moving the image horizontally.
OPTIONS



[ندعوك للتسجيل في المنتدى أو التعريف بنفسك لمعاينة هذه الصورة]
The transition to the Options section appears on the screen table (see
fig.). Of the nine parameters listed in the table can be changed only
two: BB - the inclusion of a blue background with no signal and HOTEL -
ban customization programs (skipping lines in the main SETUP menu). Ie
to change the status of these parameters is enough to put in the
corresponding row 0 or 1. Other - parameters specific GPU (TDA8842).
Their optimal values ​​(see table) are established in the memory EEPROM,
and change these values ​​when the adjustments of the suppliers is not a
necessity.
TEST RGB


Section TEST RGB necessary to run a test of primary colors and used
during exercise TV. Since joining this board TV will enter this mode
automatically when the power switch ON / OFF switch on the TV. To cancel
this mode, press the MUTE button on the remote.
Section Auto-tuning is needed to fine-tune the TV to the technological
channels of the manufacturer. When work of a specialist service, this
function is not used.
Initialize EEPROM replacing chips


Setting the replacement EEPROM chips takes place automatically after 10
seconds after the TV out of standby mode. That sets the average values.
Some parameters (eg, IF-PLL) requires accurate setting, and these
operations are carried out in service mode and described above.
The sequence of operations alignment CRT TV "FALCON 54TTS6155.



[ندعوك للتسجيل في المنتدى أو التعريف بنفسك لمعاينة هذه الصورة]
1. Set the deflection system (OS) on the neck of the kinescope, and then temporarily lock the operating screw, see Figure 1.
2. Connect the wiring harness running to the connector HR401 chassis.
3. Turn on the TV and give a signal "red box".
4. Activate the image settings "STANDARD" button "FUZZY" on the remote.
5. Razmagnitte picture tube with an external loop degaussing.
6. Turn the operating system around its longitudinal axis so that the ruling party is horizontal sides of the screen.
7. Loosen with a screwdriver screw deflection system, see Figure 1.
8. Take running back so that the display will show vertical red zone.
9. Set the red zone the exact center of the screen, pushing and rotating
plates 2-pole magnets (magnets purity), and the size of the green and
blue zones must be similar, see Figure 2.

[ندعوك للتسجيل في المنتدى أو التعريف بنفسك لمعاينة هذه الصورة]
10. Slide gradually running forward so that the screen became uniformly
red. Temporarily put a rubber wedge (A) between the bulb CRT and OS at
the top point, with paper covering the sticky layer of the wedge, not to
shoot, see Figure 4. Tighten lightly screw the OS.
11. Check that the red field. Color should be clear and uniform across
the screen. With uneven color purity to podregulirovku straps 2-pole
magnets.
12. Set the TV to receive signal "net margin".
13. Rotating opposite each other a 4-pole bar magnets (see Fig. 1 and
Table 1), to reduce the red and blue vertical lines in the center of the
screen.

[ندعوك للتسجيل في المنتدى أو التعريف بنفسك لمعاينة هذه الصورة]
14. Rotate the strap together a 4-pole magnets (see Table 1.), Ie,
keeping the angle between them, to keep the red and blue horizontal
lines in the center of the screen.
15. Rotating opposite each other strap 6-pole magnets (see Table 1.),
Bring the purple (red and blue) and green vertical lines in the center
of the screen.
16. Rotating co-strap 6-pole magnets (see Table 1.), Ie, keeping the
angle between them, to keep the purple (red and blue) and green
horizontal line in the center of the screen.

[ندعوك للتسجيل في المنتدى أو التعريف بنفسك لمعاينة هذه الصورة]
17. Remove from the operating system temporarily installed earlier
rubber wedge (A, Figure 4) and by tilting the front part of the OS up or
down to achieve the best possible information, the intersecting
vertical and horizontal red and blue lines, as shown in Fig. 3. Put
temporarily (without removing the protective paper from the adhesive
layer) rubber wedges between the operating system and the kinescope in
pos. A and D (Fig. 4).

[ندعوك للتسجيل في المنتدى أو التعريف بنفسك لمعاينة هذه الصورة]
18. Tilting the front part of the OS to the right or left, get the best
information, the parallel vertical and horizontal red and blue lines, as
shown in Fig. 3. Put temporarily (without removing the protective paper
from the adhesive layer) rubber wedges poses. E and C (Fig. 4).
19. Get rubber wedges, remove their backing paper, apply silicone
adhesive to the surface of the wedges, which comes into contact with the
CRT (Fig. 1), and set them in position. B, D, F. Temporary wedges A, C,
D, E removed.
20. Record the positions of the Rings magnetostatic devices (ISU) paint.
21. Gently tighten the screw the OS Allen key, see Fig. 1.
22. For additional podsvedeniya ray picture tube at the corners, use the
plate magnets, see Fig. 1. Place these magnets between the OS and the
kinescope and moving magnet find the optimum position. Attach a magnet
with adhesive plate.
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